Epson PX-8 - Page 55

REV.-A
Handshaking is accomplished using a flipflop (FF) within the gate array. The FF signals, when it is
set,
that the main CPU may access the serial I/O (SIO) register in the gate array; the sub-CPU is is-
sued an interrupt,
when it is reset, that a command has been written to the SIO from the main
CPU, and is available
for access by the sub-CPU.
• Operation sequence
between main CPU and gate array.
1.
Main CPU reads the I/O address 05H (status register) and checks the state of bit 2 (the FF).
The bit indicates, when it is on, that the main CPU may access SIO.
2. Main
CPU reads or writes SIO (I/O address 06H).
3.
Main CPU writes bit 1 of the command register (I/O address 01 H) and sets FF.
• Operation sequence between the sub-CPU and gate array.
1. Sub-CPU waits until its port 22 goes high (this occurs when FF is reset by the main CPU), in-
dicating that main CPU has stored a command in SIO.
2. Sub-CPU issues
the shift clock (SCK) and reads in the command from SIO one bit at a time
and performs the specified processing.
3. Sub-CPU activates its
port 22 to set the FF-setting. The FF informs the main CPU that the
command has been received and the SIO is now available for access by the main CPU.
• Fig.
2-27 illustrates the interfacing operation between the main CPU and sub-CPU 7508 via the
gate array.
(RI W R (WI
R W
(RI W
Z80 data bus
Command
Data Command
Data
SID
FF resetting pulse I----~
SID ready ~--~
7508 data bus ~--~--
Ready (7508) ~---------I
Fig. 2-27 Main CPU and Sub-CPU Interfacing Signal Timing
2-31