REV.-A
2.3.2
Operations
of
Main
CPU
(70008)
The Main
CPU
Z80
operates using
control
programs
contained in
the
32kB
ROM (2A)
to
control
the
slave
CPU
6303,
sub-CPU
7508,
gate arrays, D-RAM, and serial
controller
82C51,
etc. The
slave and sub-CPUs are
controlled
via
the
handshaking gate arrays.
These
control
operations are accomplished using the
I/O
addresses listed in table 2-4.
Table
2-4
I/O
Address
I/O
adress
Read/Write
Circuit
component
Function
access
R
GAH40M
Input
Capture register
(L)
command
trigger
0000
W
GAH40M
Control register
R
GAH40M
Input
Capture register
(H)
command
trigger
0001
W
GAH40M
Command register
R
GAH40M
Input
Capture register
(L)
barcode
trigger
0002
W
GAH40M
Control register
0003
R
GAH40M
Input
Capture register
(H)
barcode
trigger
R
GAH40M
Interrupt
Status register
0004
W
GAH40M
Interrupt
Enable register
0005
R
GAH40M
Status register
R
GAH40M
Serial
I/O
register
0006
W Serial
I/O
register
0007
l
Unused
0008
OOOC
W 82C51
Command
OOOD
R/W
82C51 Data
OOOE
R SED
1320
Status
R
SED
1320
Data
OOOF
W
Command register
0010
l Unused
OOFF
2.3.2.1
Reset
Three negative going
swings
of
the
clock
signal supplied
at
the
RS
terminal cause the internal ini-
tialization
of
the
line
CPU
70008,
which
then
waits
for
the
reset
condition
to
be removed.
When
the reset signal is discontinued,
the
CPU
begins executing
its
program
from
address
OOOOH
(the
start
address
of
the
ROM located
at
2A). The internal initialization sequence occurs
as
follows:
• Resetting the Program Counter
(PC)
to
OOOOH
• Resetting
the
Interrupt
Enable
flipflop
(IFF)
to
0
• Resetting the Index register
(I)
and
the
memory
Refresh register
(R)
to
00
• Resetting the
interrupt
mode
to
0
• Forcing all address/data bus lines in the high impedance
state
• Diactivating all
control
signals
2-37
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