Epson PX-8 - Page 64

REV.-A
Table 2-7 Interrupt Request Signal and Their Priority
Interrupt
Signal name Function
Vector
Priority order address
--
Highest BURG External bus request from option unit
-
--
NMI
Unused
-
INTR (INTO)
Alarm and
low voltage detection from sub-CPU 7508 FO
INTR (INT 1)
1-byte received from serial controller 82C51
F2
INTR (lNT 2) CD signal from RS-232C interface F4
INTR (INT 3)
Barcode
trigger within gate array GAH40M
F6
INTR (lNT 4)
Free running counter
overflow within gate array GAH40M
F8
Lowest
INTR (lNT
5)
Interrupt from option unit FA
3. Intrerrupt vectors
When accepting an enabled interrupt request via the Z-INT terminal of GAH40D, the main CPU
makes an indirect call to the interrupt processing routine using the contents of the I register and
the read vector address - this call is called madkable interrupt mode 2 operation.
Fig.
2-35 shows the signal timing from the time the interrupt is accepted until the interrupt rou-
tine is entered by the indirect call. A concept of the controlling scheme is also presented.
Clock signal
Data
Address bus
Latest state
T1
T2 TW
TW T3
-_____ r---------------- ------------ ------
\ '
'- __ --1. _________________________________ _
\~------------------~/
\ /
~----:I-n-pu-Ct-d.,.-a..,..ta---
(vector address)
----------------~< r-
__________ -'Xl... ____________________ --'x Memory refresh
Upper
7 bits of
input data
I
/
Interrupt routine
start address table}/
~ ___ ~~Loweraddress
bits
'---- ________ ~ Upper addre.ss
__ j;)rts
Interrupt service
Routine
Fig. 2-35 Interrupt Routine Call Control and Timing
2-40