Epson PX-8 - Page 75

REV.-A
The primary and divided frequency
output signal waveforms are as
shown in Fig. 2-49.
The 2.45 MHz clock signal is sup-
plied
to the main CPU (4A), gate ar-
ray
GAH40M (4A), and serial con-
troller (2C), and used as their basic
clocks.
5V
200nS
9.8M
lITDnnnnnnnnnnnnnnnnnl
G
4.9M
G
2.45: J 0 0 0 0 [
5V 5V
Fig. 2-49 CR1 Clock Signal Waveforms
The 4.9 MHz clock signal is supplied to the LCD controller (7C) and used as the basic clock signal
for LCD display control. This signal is further halved within the controller. The output clock signal
of 2.45 MHz is fed to the external clock signal input terminal (EXTAL) of the 6303 slave CPU.
Thus,
the signal is quartered within the slave CPU to a clock signal of 614 kHz and used as its
operation clock signal.
2V
50mV
lOOnS
5V
5V
500nS
6303
f\MMN\MMN
l/1Jillill
EXTAL
4.9M
G
6303
b
b
LL
E
G
G
~
r
\f\f\
6303
0
[
6303
AS
n
0
EXTAL
G
G
2V
5V
500mV
Fig. 2-50 LCD Controller and Slave CPU Operation Clock Signal Waveforms
2-51