FLIR LEPTON® Engineering Datasheet
The information contained herein does not contain technology as defined by the EAR, 15 CFR 772, is publicly available,
and therefore, not subject to EAR. NSR (6/14/2018).
Information on this page is subject to change without notice.
Lepton Engineering Datasheet, Document Number: 500-0659-00-09 Rev: 203
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Table 8 - Lepton Camera Module Pin Description for VPROG
4.2 VoSPI Channel
The Lepton VoSPI protocol allows efficient and verifiable transfer of video over a SPI channel. The protocol is
packet-based with no embedded timing signals and no requirement for flow control. The host (master) initiates
all transactions and controls the clock speed. Data can be pulled from the Lepton (the slave) at a flexible rate. This
flexibility is depicted in Figure 16, which shows the use of a relatively slow clock utilizing most of the available
frame period as well as the use of a fast clock that bursts frame data. Once all data for a given frame is read, the
master has the option to stop the clock and/or de-assert the chip select until the next available frame.
Alternatively, the master can simply leave the clock and chip select enabled, in which case Lepton transmits
discard packets until the next valid video data is available.
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