Troubleshooting
Troubleshooting the Digital Section
5
5-7
A0-A15,
DS*, PS*, X/Y*
CS_BOOTROM
CLOCK
AD
DATA
0 ns 100 ns 200 ns 300 ns
Address Bus, DS, PS, XY
15 Min/Max
285.46 Min/Max
125 Min/Max
250 Min/Max
281.96 Min/Max
263.15 Min/Max
15 Min/Max
6.20 Min/Max
5.05 Min/Max
0
t16i.eps
A0-A15, DS*, PS*, X/Y*
CS_SRAM
CLOCK
RD
DATA
0 ns 50 ns 100 ns
48.63 Min/Max
8 Min
45.13 Min/Max
26.32
Min/Max
6.20 Min/Max
5.05 Min/Max
25 Min
15
Min/Max
0
25 Min
15
Min/Max
Address Bus, DS, PS, XY
t17i.eps
If these signals are not correct, verify that the appropriate signals (A15, A14, A5, A4,
RD, WR, XY, PS) are present and correct. If these signals are not correct, you may have
a problem with the DSP chip (U2). If these signals are correct, you may have a problem
with U3.
5-7. Troubleshooting the A/D Converter Output
To isolate a problem with the a/d converters, proceed as follows:
1. Check that SC0, SC2, SCK, and SRD at U2 are correct.
• SC0 (U2-29) labeled ‘CHL’ - controls which A/D converter is being read.
• SC2 (U2-32) labeled ‘FSO’ - Generates a one-bit pulse at the start of each A/D
word, and it occurs at twice the sample rate of an A/D converter.
• SCK (U2-31) labeled ‘SCK’ - Bit clock rate of the A/D converters.