8600
A
(R46, R37, R47, and
R38)
selected
by
the
range relays.
The
positive half of the
signal applied to CR1
2 is
distorted
by
the
action of
Q7
and CL1. CL1 presents a variable load
to
Q7
so that for the
positive half cycle, as
Q7
draws less
current, the voltage
on the collector of
Q7
rises more
rapidly than it
would with a purely resistive load.
The
distortion
is introduced to minimize errors
in small signal
measurements caused
by
the turn-on time of CR12.
The distortion
is
removed
for feedback purposes by the
arrangement of R51
,
C16, and R26.
During
autozero
the
A/D Converter is referenced
to
the offset
voltage (stored
on capacitors) created
by the bias
requirements
of the
circuit. The offset
voltage reference is protected from over-
voltage
conditions
by
Q8
and
Q9.
3-33.
CURRENT
SHUNT
3-34.
The Current
Shunt
produces
an output voltage
(ac
or dc) proportional
to the
current
(ac
or
dc)
applied to
the input. A
schematic diagram of the Current Shunt is
located
in Figure
8-1
.
3-35.
The Current
Shunt consists of series connected
shunt resistors
R13,R14,
R15,R16, and R2, contacts of
range
switches
S6 through
S10,
and input protection
com-
ponents
FI,
CR1,
CR2, CR6 and CR8. The input current
is applied
across
a
portion of the
shunt
resistor network via
contacts
of
the
selected range switch. The voltage
developed
by the current
flow
through
the shunt resistance for direct
current
inputs is applied
to the A-D Converter; for alternat-
ing current
the developed
ac
voltage
is
applied to
the AC
Converter.
3-36.
The
Current
Shunt is
not only protected against
inputs
exceeding two amperes,
as
provided by fuse
FI
,
it is
also protected from
possible
damage caused
by
an overrange
input. Diodes
CR1, CR2, CR6, and CR8
will start
to
con-
duct if the voltage drop
across the shunt resistors
exceeds
1 .2 volts.
3-37.
A/D
Converter
3-38.
The
A-D
Converter
uses a dual-slope conversion
technique.
The dc voltage
at the input of the A-D Con-
verter
is integrated
(charges
a capacitor)
for
a controlled
amount of time
(100
ms).
The level to which
the
capacitor
is charged
is directly
proportional to the level of dc voltage
applied
to
the input.
The
charged capacitor
is then discharg-
ed at
a controlled
rate
so that
the discharge
time is pro-
portional
to the level
of charge on the capacitor. The dis-
charge
time is measured
by
counting the number of cycles
of
a
reference
frequency
that
occur
from the
start
of dis-
charge to
the point where
the capacitor reaches a selected
zero detect
level.
Figure
3-5
is
a
basic illustration
of the
A-D
Converter. The Input
Divider is shown as the
A-D
Converter
input voltage
source.
3-39
The
dc
voltage from
the input divider is gated
through
Q14
to the noninverting
input of
buffer,
U4, by
the
100msec
integrate
(INT) control signal. The output
of
U4 is applied to the inverting
input of integrator, U5.
C28 is charged
by U5 and U4 through
R80,
except that
in
the
lowest range the
charge path
is through R66 and
R80.
The slope
of the
output voltage
from U5 is
propor-
tional
and opposite in polarity
to the level of the
dc
voltage
from the input divider. The output
of U5 is applied to
the
input
of comparator,
U6. As
the
output of U5 changes
away from
OV,
the output of
U6 changes from random
noise to a steady state of either
OV or +5V, depending on
the
polarity of the dc voltage from the input divider.
At
the end of the
integrate
period
Q14
is
turned off,
U4
and
U5 no longer
charge
C28, and
the charge on
C28
is
held.
Also
at
the end of the integrate
period,
the
state of the
output of
U6
is memorized in the DVM IC,
U8.
An
appro-
priate read
reference is selected in
U8.
DE(+R) is
selected for negative
voltages from
the
input divider,
or
DE(-R)
is
selected
for positive voltages. DE(+R)
enables
Q16,
which
applies the +1V reference from U17
to the
input of U4. DE(-R)
enables
Q21
,
which
applies the
—IV
charge on
C22
to the input of
U4 (in the
lowest range
+
.1
V
is selected as
the reference). A delay of
15
jusec is
introduced in U8
between application of the read
reference
and the
start
of the counter.
The delay allows adjustment
of the zero detect level for
comparator,
U6.
The read
reference
voltage applied
to
U4
allows U4 and U5 to
dis-
charge
C28.
The slope
of the output of
U5 is
always the
same
for
the reference applied (IV
or .IV). The charge on
C28 is
proportional
to the voltage
from the
input
divider.
Therefore the time required
to discharge
C28
is propor-
tional
to the
voltage
from the input divider. When
the
output of
U5
crosses the zero
detect level, the output of
U6
changes state, producing
the compare output applied
to U8. The compare
signal
stops
the counter in U8.
The
number of counts is proportional to
the
voltage
from
the
input divider.
340. After the
A-D
Converter
has integrated the
unknown
input
voltage, integrated the reference
voltage, and
produced
the compare output; the circuits
of the converter
are zeroed
for a new measurement. An auto
zero
(AZ) control signal
from U8 will enable
Q15
and
Q22
to zero the
comparator
circuits. The AZ
control signal will
also
enable
Q
17 to
charge
capacitor
C22
to the reference voltage
level. This
provides
the negative reference voltage,
when
Q21
is
enabled,
needed
to process
a
positive input
voltage.
341 The different zero detect
levels applied to U6
compensate for the
1
5
psec delay introduced at the end
of the
integrate period.
The
delay
and subsequently
different zero detect levels
are used
to
facilitate
a
solid
zero display in the presence
of noise with no input. Also
errors due
to noise are minimized. The zero detect levels
are determined
by the logic levels of the read reference
switches and the associated resistive network.
3-6
1/77
To Next Page
Loading...
