USB 3.0 Hub Design Guide
© 2015 Genesys Logic, Inc. - All rights reserved. Page 4
GLI Confidential
Table of Contents
1. INTRODUCTION .............................................................................................................. 6
2. CIRCUIT DESIGN AND PCB LAYOUT GUIDELINES ............................................. 6
2.1 AC Coupling Capacitors ........................................................................................... 6
2.2 PCB Layer and Material ........................................................................................... 7
2.2.1 4-Layer PCB ................................................................................................... 7
2.2.2 2-Layer PCB ................................................................................................... 7
2.3 Differential Pairs Trace ............................................................................................. 7
2.3.1 Differential Pair Impedance .......................................................................... 7
2.3.2 Differential Trace ........................................................................................... 7
2.3.3 Differential Trace Length Preliminary Guidelines ..................................... 7
2.3.4 Trace Bend ...................................................................................................... 8
2.3.5 Reference Plane .............................................................................................. 8
2.3.6 Signal Return Path ......................................................................................... 9
2.3.7 Differential Pair Layout .............................................................................. 11
2.3.8 Avoid Stub on Differential Traces .............................................................. 12
2.3.9 SS Trace Swap .............................................................................................. 12
2.4 Circuit and Component Placement ........................................................................ 14
2.4.1 Decoupling Capacitors ................................................................................. 14
2.4.2 RTERM Resistor .......................................................................................... 14
2.4.3 Crystal Circuit .............................................................................................. 15
2.4.4 Reset Circuit ................................................................................................. 15
2.5 Power Source ............................................................................................................ 16
2.6 Power Trace of Charging Downstream Port ......................................................... 17
2.7 Thermal Reduction .................................................................................................. 17
2.8 Trace Width and Adjacent Space Gap .................................................................. 18
2.8.1 USB 3.0 .......................................................................................................... 18
2.8.2 USB 2.0 .......................................................................................................... 18
2.8.3 Recommend Width and Space for USB 2.0 & USB3.0 Trace .................. 18
2.9 GL3520/GL3521 Co-Layout Notice ....................................................................... 19
2.10 GL3521 Layout Notice ............................................................................................. 20
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