Gigabyte MS04-CE0 - Page 16

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Hardware Installation
Intel Xeon 6500P/6700P-Series Memory Support
Type
Ranks Per
DIMM and
Data Width
DIMM Capacity (GB)
Channel Speed (MT/s); Voltage (V);
Slots per Channel (SPC) & DIMMs per
Channel Density (DPC)
DRAM Density
16Gb 24Gb 32Gb 1DPC/2SPC 2DPC/2SPC
1DPC 2DPC 1DPC 2DPC 1DPC 2DPC 1.1V
RDIMM
1Rx8 16GB 24GB 6400, 6000,
5600, 5200, 4800
(DDR5-6400
rated RDIMMS
only)
5200, 4800
(DDR5-6400 rated
RDIMMS only)
1Rx4 32GB 48GB
2Rx8 32GB 32GB 48GB
2Rx4 64GB* 64GB*^ 96GB* 96GB*^ 128GB* 128GB*^
RDIMM 3DS 8Rx4 256GB*
MRDIMM
2Rx8 32GB 8000, 7200
(MRDIMM-8800 only)
N/A (no 2DPC
congs for MRDIMM)
2Rx4 64GB
NOTE:
• *Supported in 1S/2S/4S systems
• ^Supported in 8S systems
Intel Xeon 6500P/6700P-Series CXL Memory Support
Native DDR5 Memory Per
Socket
CXL Memory Per Socket
Slot0 DIMM
Ranks
Slot0 DIMM
Capacity (GB)
DIMM
Type
DRAM
Density
(Gb)
CXL Memory
Channels
CXL Memory
Type
CXL Capacity
Per Device/
Module
CXL
Interleave
CXL Mode
4S &8S
Support
2Rx4 96 10x4 24 2+2 DDR5 x8 96 GB# 1x4*, 2x2, 4x1 1LM+Vol Yes
2Rx4 128 10x4 32 2+2
DDR4x8#
DDR5 x8
128 GB 1x4*, 2x2, 4x1 1LM+Vol Yes
2Rx4 128 10x4 32 2+2 DDR5 x8 128 GB hetero x12 Hetero Yes
2Rx4 64 10x4 16 2+2+2 DDR5 x8 128 GB 1x6*, 2x3, 3x2 1LM+Vol No
2Rx4 64 10x4 16 2 DDR5 x8 128 GB 1x2* 1LM+Vol No
2Rx4 64 10x4 16 1+1 DDR5 x16 2ch 128 GB 1x2*
Intel® Flat
Memory
Mode
No
NOTE:
• Xeon 6500P/6700P-series processors CXL memory congs are 1DPC (‘Slot 0’) only for native DDR5
• CXL Memory Channel notation: # of devices per root port, with root ports separated by “+”. i.e. 2+2+2+2
= four root ports populated with two devices per root port
• CXL Interleave notation: sets x ways. i.e. 2x4 = Set of two modules, interleaved four-way
• CXL Modes:
• 1LM+Vol = Native DDR5 (‘1LM’) and (volatile) CXL memory visible to SW as separate tiers,
separately interleaved
• Hetero x12 = DDR5 and (volatile) CXL memory interleaved together in one 12-way set (See graphic
in next slide)
• Flat Memory Mode = HW manages data movement between DDR5 and CXL memory, total capacity
visible to SW