EasyManua.ls Logo

GigaDevice Semiconductor GD32450Z-EVAL - USART Interface Schematic; ADC Circuit Schematic; DAC Circuit Schematic

Default Icon
53 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
User Guide
GD32450Z-EVAL
12
4.5. USART
Figure 4-5 Schematic diagram of USART0 function
C1+
1
V+
2
C1-
3
C2+
4
C2-
5
V-
6
T2OUT
7
R2IN
8
R2OUT
9
T2IN
10
T1IN
11
R1OUT
12
R1IN
13
T1OUT
14
GND
15
VCC
16
U3
MAX3232CSE+
+3V3
GND
C24
50V/0.1uF
C26
50V/0.1uF
C25
50V/0.1uF
C23
50V/0.1uF
C22
50V/0.1uF
GND
USART0_TX
USART0_RX
1
6
2
7
3
8
4
9
5
J1
COM0
GND
USART0
PA10
RS232_TX0
RS232_RX0
PA9
4.6. ADC
Figure 4-6 Schematic diagram of ADC function
+3V3
GND
ADC
C28
50V/0.1uF
R10
49.9Ω
PF6
VR1
1K
1
TP2
TP ADin
ADC012_IN4
4.7. DAC
Figure 4-7 Schematic diagram of DAC function
DAC
DAC_OUT0
PA4 is an AFIO, please refer to TLI Schematic for right config
PA4
GND
1
2
JP5
DAC