GW Instek APS-7100 - Status Byte Register & Service Request Enable Register

REMOTE CONTROL
139
Status Byte Register & Service Request Enable Register
Overview
The Status Byte register consolidates the status
events of all the status registers. The Status Byte
register can be read with the *STB? query and can
be cleared with the *CLS command.
WAR
ERR
QUES
MAV
ESB
MSS
OPER
0
1
2
3
4
5
6
7
Output
Buffer
:
:
:
Error Que
:
:
:
Status
Byte
Register
0
1
2
3
4
5
6
7
&
&
&
&
&
&
&
*SRE <NRf>
*SRE?
Service
Request
Enable
Register
Logical OR
*STB?
From Operation
Status Register
From
Questionable
Status Register
From Standard
Event Status
Register
From Warning
Status Register
Bit Summary
Event
Bit #
Bit
Weight
WAR (Warning Status Register)
The summary bit for the Warning
Status Register group.
1
2
ERR (Error Event/Queue)
If data is present in the Error
queue, the ERR bit will be set.
2
4
QUES (Questionable Status
Register)
The summary bit for the
Questionable Status Register
group.
3
8