Hitachi DK23DA-20F - Page 107

K6602705
Rev.3
08.20.01
- 107 -
Figure 6-16 Host terminating an Ultra DMA Write
DMARQ
(device)
DMACK-
(host)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2,
CS0-, CS1-
t
ACK
t
LI
t
MLI
t
CVS
t
LI
t
LI
t
ACK
t
IORDYZ
t
ACK
CRC
t
CVH
t
SS
Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect
after DMARQ and DMACK are negated.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode 3(ns) Mode 4(ns) Mode5(ns) Description
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t
CVS
70 48 31 20 6.7 10 CRC word valid setup time
at sender
t
CVH
6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold time at
sender
t
LI
0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time
t
MLI
20 20 20 20 20 20 Interlock time with minimum
t
AZ
10 10 10 10 10 10 Maximum time allowed for
output drivers to release
t
IORDYZ
20 20 20 20 20 20 Maximum time before
releasing IORDY
t
ACK
20 20 20 20 20 20 Setup and hold times for
DMACK_
t
SS
50 50 50 50 50 50 Time from STROBE ed
g
e
to ne
g
ation of DMARQ or
assertion of STOP