HP Compaq dc7600 MT Technical Reference Guide

4-14 www.hp.com Technical Reference Guide
System Support
Maskable Interrupt processing is controlled and monitored through standard AT-type
I/O-mapped registers. These registers are listed in Table 4-8.
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may
be maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
■
Parity errors detected on a PCI bus (activating SERR- or PERR-).
■
Microprocessor internal error (activating IERRA or IERRB)
The SERR- and PERR- signals are routed through the ICH8 component, which in turn activates
the NMI to the microprocessor.
Table 4-8.
Maskable Interrupt Control Registers
I/O Port Register
020h Base Address, Int. Cntlr. 1
021h Initialization Command Word 2-4, Int. Cntlr. 1
0A0h Base Address, Int. Cntlr. 2
0A1h Initialization Command Word 2-4, Int. Cntlr. 2

HP Compaq dc7600 MT Specifications

General

Memory	Up to 4 GB DDR2 SDRAM
Audio	Integrated High Definition Audio
Expansion Slots	1 PCI Express x16, 1 PCI Express x1, 2 PCI
Form Factor	Microtower
Processor	Intel Pentium 4 or Intel Celeron D
Chipset	Intel 945G Express
Hard Drive	40 GB to 160GB SATA
Optical Drive	DVD-ROM, DVD+/-RW
Graphics	Integrated Intel Graphics Media Accelerator 950
Networking	Integrated 10/100/1000 Ethernet
Ports	Serial, parallel, VGA, audio in/out
Operating System	Windows XP Professional, Windows XP Home
USB Ports	8 USB 2.0 (2 front, 6 rear)