IBM Power 750 - Page 196

182 IBM Power 750 and 760 Technical Overview and Introduction
Optional ECC I/O hub with freeze behavior X X X X X X X
PCI bus extended error detection X X X X X X X
PCI bus extended error recovery X X X X Most Most Most
PCI-PCI bridge Enhanced Error Handling X X X X - - -
Redundant RIO or 12x Channel link
a
XXXXXX X
PCI card hot-swap XXXXXX X
Dynamic SP failover at run time
b
XXXXXX X
Memory sparing with CoD at IPL time X X X X X X X
Clock failover run time or IPL
b
XXXXXX X
Memory availability
ECC memory, L2, L3 cache X X X X X X X
CRC plus retry on memory data bus X X X X X X X
Data Bus XXXXXX X
Dynamic memory channel repair X X X X X X X
Processor memory controller memory scrubbing X X X X X X X
Memory page deallocation X X X X X X X
Chipkill memory XXXXXX X
L1 instruction and data array protection X X X X X X X
L2/L3 ECC and cache line delete X X X X X X X
Special uncorrectable error handling X X X X X X X
Active Memory Mirroring for Hypervisor
b
XXXXXX X
Fault detection and isolation
Platform FFDC diagnostics XXXXXX X
Run-time diagnostics X X X X Most Most Most
Storage Protection Keys - X X X - - -
Dynamic Trace X X X X - - X
Operating System FFDC - X X X - - -
Error log analysis XXXXXX X
Freeze mode of I/O Hub X X X X - - -
Service processor support for:
򐂰 Built-in self-tests (BIST) for logic and arrays X X X X X X X
򐂰 Wire tests XXXXXX X
򐂰 Component initialization X X X X X X X
RAS feature
AIX
5.3
AIX
6.1
AIX
7.1
IBM i RHEL
5.7
RHEL
6.3
SLES11
SP2