IBM Power 750 - POWER7+ Processor Overview

46 IBM Power 750 and 760 Technical Overview and Introduction
Figure 2-2 POWER7+ processor die with key areas indicated
2.1.1 POWER7+ processor overview
The POWER7+ processor chip is fabricated with IBM 32 nm Silicon-On-Insulator (SOI)
technology using copper interconnects, and implements an on-chip L3 cache using eDRAM.
The POWER7+ processor chip is 567 mm
2
and has 2.1 billion components (transistors). Up
to eight processor cores are on the chip, each with 12 execution units, 256 KB of L2 cache
per core, and up to 80 MB of shared on-chip L3 cache per chip.
For memory access, the POWER7+ processor includes a double data rate 3 (DDR3) memory
controller with four memory channels.
Table 2-1 summarizes the technology characteristics of the POWER7+ processor.
Table 2-1 Summary of POWER7+ processor technology
Technology POWER7+ processor
Die size 567 mm
2
Fabrication technology 򐂰 32 nm lithography
򐂰 Copper interconnect
򐂰 Silicon-on-Insulator
򐂰 eDRAM
Processor cores 3, 4, 6, or 8