IBM Power 750 - On-Chip L3 Cache Innovation and Intelligent Cache

Chapter 2. Architecture and technical overview 49
Figure 2-4 gives a simple overview of the POWER7+ processor memory access structure in
the Power 750 and Power 760 systems.
Figure 2-4 Overview of POWER7+ memory access structure
2.1.5 On-chip L3 cache innovation and Intelligent Cache
A breakthrough in material engineering and microprocessor fabrication enabled IBM to
implement the L3 cache in eDRAM and place it on the POWER7+ processor die. L3 cache is
critical to a balanced design, as is the ability to provide good signaling between the L3 cache
and other elements of the hierarchy, such as the L2 cache or SMP interconnect.
The on-chip L3 cache is organized into separate areas with differing latency characteristics.
Each processor core is associated with a fast local region of L3 cache (FLR-L3) but also has
access to other L3 cache regions as shared L3 cache. Additionally, each core can negotiate
to use the FLR-L3 cache associated with another core, depending on reference patterns.
Data can also be cloned to be stored in more than one core’s FLR-L3 cache, again depending
on reference patterns. This
Intelligent Cache management enables the POWER7+ processor
to optimize the access to L3 cache lines and minimize overall cache latencies.
Buffer
Port A
Port B
DDR3 RDIMM Slot 7
DDR3 RDIMM Slot 8
DDR3 RDIMM Slot 1
DDR3 RDIMM Slot 2
Buffer
Port A
Port B
DDR3 RDIMM Slot 5
DDR3 RDIMM Slot 6
DDR3 RDIMM Slot 3
DDR3 RDIMM Slot 4
Buffer
Port A
Port B
DDR3 RDIMM Slot 5
DDR3 RDIMM Slot 6
DDR3 RDIMM Slot 3
DDR3 RDIMM Slot 4
Buffer
Port A
Port B
DDR3 RDIMM Slot 7
DDR3 RDIMM Slot 8
DDR3 RDIMM Slot 1
DDR3 RDIMM Slot 2
P3-Cn-C7
P3-Cn-C8
P3-Cn-C1
P3-Cn-C2
P3-Cn-C5
P3-Cn-C6
P3-Cn-C3
P3-Cn-C4
P3-Cn-C7
P3-Cn-C8
P3-Cn-C1
P3-Cn-C2
P3-Cn-C5
P3-Cn-C6
P3-Cn-C3
P3-Cn-C4
POWER7+
DCM
P7+ Chip1
Channel D
P7+ Chip1
Channel C
P7+ Chip0
Channel B
P7+ Chip0
Channel A