Chapter 2. Architecture and technical overview 53
The previous POWER7 technology-based Power 750 (8233-E8B) uses a single node design.
It was available as a 4-socket system with one POWER7 chip per socket and W-Y-Z buses
between sockets, as shown in Figure 2-7. A 6-core or 8-core POWER7 chip was orderable.
Figure 2-7 Intra-node buses
The POWER7+ technology-based Power 750 (8408-E8D) and Power 760 use a multiple
node design, with two POWER7+ chips per socket delivered in a dual chip module package
(DCM). The Power 750 (8408-E8D) can be ordered with a 4-core chip and the Power 760 can
be ordered with a 6-core chip. The two POWER7+ chips within the DCM communicate using
the Y-Z bus architecture that was previously deployed between sockets in the POWER7
technology-based Power 750 (8233-E8B). However, communications between DCMs, from
socket to socket, use AB buses as illustrated in Figure 2-8.
Figure 2-8 Inter-node buses
From a topology standpoint, the new Power 750 (8408-E8D) and Power 760 (9109-RMD)
systems are similar to the 4-CEC enclosure Power 770 and Power 780 systems. In this case,
the interconnects between chips in a DCM of a Power 750 (8408-E8D) and Power 760
(9109-RMD) server are similar to the interconnects that are used between sockets in a single
Power 770 or Power 780 system enclosure. Similarly, the interconnects between DCMs in the
four sockets of the Power 750 (8408-E8D) and Power 760 (9109-RMD) system are similar to
the interconnects that are used between the system enclosures of a Power 770 or Power 780.
This architecture provides the best bandwidth and lowest latency between the chips within a
DCM or socket (node) and a lower bandwidth and higher latency between DCMs or sockets
(nodes). Therefore, when configuring workloads that span the DCM or socket (node)
boundaries within a Power 750 (8408-E8D) and Power 760 (9109-RMD), the same
Node
Node
Node
Node
P7
P7
P7
P7
P7
P7
P7
P7
AB Buses
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