VDDC voltage has reached above +2.5V and caused a reset.
The flag is typically interrogated to determine if a reset was
caused by the chip’s high voltage when the voltage monitor
is enabled. (Normally enabled when the security lock bit is
locked by the ROM Loader.) This flag must be cleared by
software once set, otherwise this bit is unaffected by any
other resets except BOR. Setting of this bit by software will
not generate a reset.
Voltage Glitch Failure. When set, this bit indicates that the
enabled (GLIEN = 1) voltage glitch monitor has detected a
1.5V negative/positive glitch from VDDIO or VDDC that
exceeded 20 ns in duration and caused a reset. It is typically
interrogated to determine if a reset was caused by voltage
glitch when the glitch monitor is enabled. This flag must be
cleared by software once set, otherwise this bit is
unaffected by any other resets except BOR. Setting of this
bit by software will not generate a reset.
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