IDTECH SREDKey - Magstripe Reader Operation; Initial Swipe and Key-in Procedure; Function Key Operations Guide

5
HBF
High Battery Voltage Flag. When set, this bit indicates that
the enabled (TMPENH = 1) high battery voltage monitor has
detected the battery voltage has reached above +4 V and
caused a DRS. The flag is typically interrogated to determine
if a DRS was caused by the battery voltage being too
high.(Normally it is enabled when the security lock bit is
locked by the ROM Loader.) This flag must be cleared by
software once set, otherwise this bit is unaffected by any
other resets except BOR. Setting of this bit by software will
not generate a DRS.
LBF
Low Battery Voltage Flag. When set, this bit indicates that
the enabled (TMPENL = 1) low battery voltage monitor has
detected the battery voltage has reached below 2.2 V and
caused a DRS. This bit is typically interrogated to determine
if a DRS was caused by the battery voltage being too low.
(Normally it is enabled when the security lock bit is locked
by the ROM Loader.) This flag must be cleared by software
once set, otherwise this bit is unaffected by any other resets
except BOR. Setting of this bit by software will not generate
a DRS.
SDI1
SDI1 Flag. When set, this bit indicates that the external
tamper detection circuitry has been triggered and caused a
DRS by activating SDI1. The flag is typically interrogated to
determine if a DRS was caused by the SDI1. The SDI1 input
can be configured to be a normally open connection
(internal pull down resistor is in effect) or normally closed
connection (internal pull-up resistor is in effect), based
upon the SECNT.SDI1C configuration bit. This flag must be
cleared by software once set, otherwise this bit is
unaffected by any other resets except BOR. Setting of this
bit by software will not generate a DRS or reset
SDI2
SDI2 Flag. When set, this bit indicates that the external
tamper detection circuitry has been triggered and caused a
DRS by activating SDI2. The bit is typically interrogated to
determine if a DRS was caused by the SDI2. The SDI2 input
can be configured to be a normally open connection
(internal pull down resistor is in effect) or normally closed
connection (internal pull-up resistor is in effect) based upon
the SECNT.SDI2C configuration bit. This flag must be cleared
by software once set, otherwise this bit is unaffected by any
other resets except BOR. Setting of this bit by software will
not generate a DRS or reset.
HVF1
High VDDC Flag. When set, this bit indicates that the
enabled (HIVOLEN = 1) voltage monitor has detected the