Ingenic Halley5 - Page 8

Halley5 Core board
X2000 Development Kit User Manual
Copyright® 2005-2021 Ingenic Semiconductor Co., Ltd. All rights reserved.
5
Figure 2-1 Halley5 Core Board Power Circuit
R2
100k
C75
10uF
3V3P
R13
100k
VSYS
C41
10uF
VSYS 1V8P
R56 10
R57 10
L4 1.5uH
L2 1.5uH
IOUT max=2A
1V8P
C27
10uF
IOUT max=3A
1V2P
C26
10pF
R5
100K/1%
R7
100K/1%
VSD18_EN
These two prob points are from CPU side
C25
10uF
C34
10uF
C92
10uF
C42
10pF
R12
200K/1%
VSYS
R14
100K/1%
R6
10k
VSD18_EN
PWRON
3V3P
Q12
WPM2031
3
1
2
VDDIO_SD
C43
10uF
U11
G2257Q51U
GND3
1
FB3
2
VCC
3
AGND
4
FB2
5
GND2
6
LX2
7
VIN2
8
EN2
9
EN1
10
VIN1
11
LX1
12
LDOIN
18
FB4
17
LDOO
16
LDOFB
15
FB1
14
ENLDO
13
LX3
24
VIN3
23
EN3
22
EN4
21
VIN4
20
LX4
19
EP
25
3V3P
C72
1uF
C73
10uF
C74
10uF
VDDIO_SD
C103
10uF
IOUT max=2A
C8 10pF
3V3P
L1
1.5uH
C9
10uF
R1
453K/1%
R3
100K/1%
R55
NC
L3 1.5uH
C32
10pF
R8
100K/1%
R10
200K/1%
0V9P
IOUT max= 3A
R43 100K/1%
C7
10uF
VSYS
C33
10uF
1V8P
R9
100k
0V9P
VSYS
R44
200K/1%
C47
1uF
C46
1uF
C51
1uF
C50
1uF
U6
RT9078N-08GJ5
EN
3
GND
2
SNS
4
VIN
1
OUT
5
R15
182K/1%
U7
RT9078-18GJ5
EN
3
GND
2
NC
4
VIN
1
OUT
5
C45
56pF/NC
VDDRTC
VDDIORTCVBATRTC VDDIORTC
R48
NC
R4 240 1%
C35
1uF
C36
0.1uF
C17
1uF
C18
0.1uF
FB13 FB
DDR
CORE
IO
CIM
SD
RTC
PLL
EFUSE
VSS
U1B
X2000_V1.0
VDD_0
F8
VDD_1
F9
VDD_4
G8
VDD_5
G9
VDD_6
G11
VDD_7
G12
VDD_8
H11
VDD_9
H12
VDD_10
K7
VDD_11
K8
VDD_12
K11
VDD_13
K12
VDD_14
L7
VDD_15
L8
VDD_16
L11
VDD_18
L12
VDD_19
M11
VDD_20
M12
VDDIO_0
G6
VDDIO_1
H6
VDDIO18_0
J13
VDDIO18_1
N12
VDDIO33_0
H13
VDDIO33_1
N13
VDDMEM_0
A9
VDDMEM_1
B8
VDDMEM_2
B9
VDDMEM_3
C8
VDDMEM_4
C9
VDDMEM_5
C12
VDDMEM_6
C13
VDDMEM_7
D12
VDDMEM_8
D13
AVDEFUSE
D5
VSS_0
A8
VSS_1
A13
VSS_2
B10
VSS_3
B13
VSS_4
C7
VSS_5
C11
VSS_6
D7
VSS_7
D8
VSS_8
D9
VSS_9
D10
VSS_10
D11
VSS_11
F6
VSS_12
F7
VSS_13
F10
VSS_14
F13
VSS_15
G7
VSS_16
G10
VSS_17
G13
VSS_18
H7
VSS_19
H8
VSS_20
H9
VSS_21
H10
VSS_22
J6
VSS_23
J7
VSS_24
J8
VSS_25
J11
VSS_26
J12
VSS_27
K6
VSS_28
K13
VSS_29
L6
VSS_30
L9
VSS_31
L10
VSS_32
L13
VSS_33
M7
VSS_34
M8
VSS_35
M9
VSS_36
M10
VSS_37
M13
VSS_38
N7
VSS_39
N10
VSS_40
N11
PLL_AVDD
H2
PLL_AVSS
J4
PLL_VDD
J3
PLL_VSS
K3
DDRPLL_VCCA
A12
DDR_VSSA
B12
DDR_VDD1_0
A11
DDR_VDD1_1
B11
VREF
A10
ZQ
C10
VDD_2
F11
VDD_3
F12
VDD_RTC
H3
VDDIO_RTC
F1
VSS_RTC
H4
VDDIO33_CIM
M6
VDDIO18_CIM
N6
VDDIO33_SD
N9
VDDIO18_SD
N8
3V3P
1V8P
C16
1uF
C15
0.1uF
R45 0
C13
1uF
C12
0.1uF
R46 NC
FB1 FB
FB2 FB
C10
0.1uF
C85
0.1uF
C86
0.1uF
C87
10nF
0V9P
1V2P
C37
0.1uF
DDR_VREF
1V8P
1V8P
C2
1uF
C88
10uF
C84
0.1uF
C89
0.1uF
C90
10nF
C11
1uF
C91
0.1uF
VDDIO_CIM
C38
0.1uF
VDDRTC
VDDIO_SD
VDDIORTC
3V3P
C39
1uF/NC Q1
WPM2031/NC
3
1
2
EFUSE_N
C1
10uF
C3
0.1uF
C19
10uF
C20
0.1uF
C21
10uF
C22
0.1uF
C6
1uF
C23
10nF
C24
10nF
R17
10k/1%
R16
10k/1%
C48
1uFC49
0.1uF
C44
0.1uF
C4
0.1uF
C5
10nF
1V8P
DDR_VREF
1V8P
C28
1uF
C29
0.1uF
1V8P
1V8P
0V9P
C14
1uF
1V8P
R11
100k/NC
C30
1uF
C31
0.1uF
1V2P
R54
1K