8. Peripherals and Options
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Extension Differential PG Card With Frequency Dividing (MD38PG6, MD38PG6D)
Table 8-20 Terminal descriptions of MD38PG6 and MD38PG6D
Terminal Pin Denition Function Description Pin Arrangement
J3 1
A+ Encoder output signal A positive
1
2
3
4
5
6
7
8
9
A+
A-
NC
+5V
B+
COM
B-
Z-
Z+
2
A- Encoder output signal A negative
3
B+ Encoder output signal B positive
4
B- Encoder output signal B negative
5
Z+ Encoder output signal Z positive
6
Null Vacant internally
7
+5V Encoder 5V power supply positive
8
COM Encoder power supply negative
9
Z- Encoder output signal Z negative
J7, J8 OA+
Frequency dividing output signal A positive
OA-
Frequency dividing output signal A negative
OB+
Frequency dividing output signal B positive
OB-
Frequency dividing output signal B negative
OZ+
Frequency dividing output signal Z positive
OZ-
Frequency dividing output signal Z negative
COM
Signal power ground
PE
Shield connecting point
CN1 18-pin FFC interface, connecting to J4 on the control board of the AC drive
● DIP Switch Setting (MD38PG6D)
DIP Swich Setting Value Frequency Dividing Coefcient DIP Switch
1 2 3 4 5
0 0 0 0 0 0 No output
ON
1
2
3
4 5
1 2 3 4 5
Frequency dividing
coefficient setting
S1
0 0 0 0 1 1 No output
0 0 0 1 0 2 Frequency divided by 4
0 0 0 1 1 3 Frequency divided by 6
…
1 1 1 1 1 31 Frequency divided by 62