DTR-5.9
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-43
Q8501 : SiI9135ACTU (HDMI Receiver)-5/5
TERMINAL DESCRIPTION
Pin Name
R0XC+
R0XC-
R0X0+
R0X0-
R0X1+
R0X1-
R0X2+
R0X2-
R1XC+
R1XC-
R1X0+
R1X0-
R1X1+
R1X1-
R1X2+
R1X2-
Pin #
40
39
44
43
48
47
52
51
58
57
62
61
66
65
70
69
Dir
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
Differential Signal Data Pins
HDMI Port 0
HDMI Port 1
Power and Ground Pins
Pin Name
CVCC18
CGND
IOVCC33
IOGND
AVCC33
AGND
AVCC18
DVCC18
DGND
XTALVCC
REGVCC
Pin #
12, 24, 25, 80, 91, 107, 119, 131, 143
11, 23, 79, 90, 106, 118, 130, 142
6, 18, 32, 74, 88, 104, 113, 125, 137
4, 17, 31, 73, 87, 103, 112, 124, 136
38, 42, 46, 50, 56, 60, 64, 68
36, 41, 45, 49, 53, 59, 63, 67, 71
37, 54, 72
92
93
96
97
Type
Power
Ground
Power
Ground
Power
Ground
Power
Power
Ground
Power
Power
Description
Digital Logic VCC.
Digital Logic GND.
Input/Output Pin VCC.
Input/Output Pin GND.
TMDS Analog VCC 3.3V.
TMDS Analog GND.
TMDS Analog VCC 1.8V.
Audio Clock Regeneration PLL.
Analog VCC. Must be connected to 1.8V.
Audio Clock Regeneration PLL.
Analog Ground.
Audio Clock Regeneration PLL
Crystal Oscillator Power. Must be connected to 3.3V.
Audio Clock Regeneration PLL.
Crystal Regulator Power. Must be connected to 3.3V.
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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