Q211: RTL8100CL (Ethernet Controller with Power Management)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -81
TX-NR905/NA905
Table 3. PCI Interface
Symbol Type Pin No Description
AD31-0 T/S 33, 34, 36, 37, 39, 40,
42, 43, 47, 49, 50, 53,
55, 57, 58, 59, 79, 82,
83, 85, 86, 87, 89, 90,
93, 95, 96, 97, 98, 103,
104
PCI Address and Data Multiplexed Pins.
C/BE3-0 T/S 44, 60, 77, 92 PCI Bus Command and Byte Enables Multiplexed Pins.
CLK I 28 Clock.
This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start
of each phase. The clock frequency ranges from 0 to 40MHz. For
normal network operation, the RTL8100C(L) requires a minimum
PCI clock frequency of 16.75MHz.
DEVSELB S/T/S 68 Device Select.
As a bus master, the RTL8100C (L) samples this signal to ensure that
a PCI target recognizes the destination address for the data transfer.
As a target, the RTL8100C(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
FRAMEB S/T/S 61 Cycle Frame.
As a bus master, this pin indicates the beginning and duration of an
access. FRAMEB is asserted low to indicate the start of a bus
transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data
phase.
As a target, the device monitors this signal before decoding the
address to check if the current transaction is addressed to it.
GNTB I 29 Grant.
This signal is asserted low to indicate to the RTL8100C(L) that the
central arbiter has granted ownership of the bus to the RTL8100C(L).
This input is used when the RTL8100C(L) is acting as a bus master.
REQB T/S 30 Request.
The RTL8100C(L) will assert this signal low to request the
ownership of the bus from the central arbiter.
IDSEL I 46 Initialization Device Select.
This pin allows the RTL8100C(L) to identify when configuration
read/write transactions are intended for it.
INTAB O/D 25 INTAB.
Used to request an interrupt. It is asserted low when an interrupt
condition occurs, as defined by the Interrupt Status, Interrupt Mask
and Interrupt Enable registers.
TERMINAL DESCRIPTION(2/4)
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TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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