Intel
®
440Bx Scalable Performance Board Development Kit Manual 21
Theory of Operation
3.2.1.2 Intel
®
Celeron™ Processor
The Intel Celeron Processor is offered at 300A, 366, 433, 566, 733 and 850 MHz. All processors
have a processor system bus speed of 66 MHz, except for the 850 MHz version, which runs at 100
MHz. Refer to the processor datasheet for processor core voltage data (see “Related Documents”
on page 10). The processor has an on-die second level cache bus that allows a high-performance
64-bit wide cache subsystem to be integrated on the same die as the processor. The processor can
cache up to 4 Gbytes of memory using 128 Kbytes of L2 cache, 16 Kbytes of L1 data cache and 16
Kbytes of L1 code cache. The on-die first and second level cache operate at the same frequency
and voltage as the processor core to improve performance and reduce total system power
consumption. Additional features include: dynamic execution technology, Intel’s MMX™ media
enhancement technology, Intel streaming SIMD extensions. At 566 MHz and higher, the processer
is available in the FC-PGA package. 433 MHz and slower Celeron processors are offered in the
PPGA package. Both packages are compatible with the 370-pin socket.
3.2.2 82443BX Host Bridge/Controller
The Intel
®
440BX AGPset supports the Pentium III processor architecture. It interfaces with the
processor system bus at 66 or 100 MHz. Along with its Host-to-PCI bridge interface, the 82443BX
Host Bridge/Controller has been optimized with a 100/66 MHz SDRAM memory controller and
data path unit. The 82443BX also features the Accelerated Graphics Port (AGP) interface. The
82443BX component includes the following functions and capabilities:
• 64-bit GTL+ based system data bus interface
• 32-bit system address bus support
• 64/72-bit main memory interface with optimized support for SDRAM
• 32-bit PCI bus interface with integrated PCI arbiter
• AGP interface with up to 133 MHz data transfer capability
• Extensive data buffering between all interfaces for high throughput and concurrent operations
3.2.2.1 System Bus Interface
The 82443BX supports a maximum of 4 Gbytes of memory address space from the processor
perspective. The largest address size is 32 bits. The 82443BX provides bus control signals and
address paths for transfers between the processor bus, PCI bus, Accelerated Graphics Port and
main memory. The 82443BX supports a 4-deep-in-order queue, which provides support for
pipelining of up to four outstanding transaction requests on the system bus.
For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the
PCI bus, depending on the PCI address space being accessed. When the access is to a PCI
configuration space, the processor I/O cycle is mapped to a PCI configuration space cycle. When
the access is to a PCI I/O or memory space, the processor address is passed without modification to
the PCI bus. Certain memory address ranges are dedicated for a graphics memory address space.
When this space or a portion of it is mapped to main DRAM, the address is translated by the AGP
address remapping mechanism and the request is forwarded to the DRAM subsystem. A portion of
the graphics aperture can be mapped on the AGP, and the corresponding system bus cycles
accessing that range are forwarded to the AGP without any translation. The AGP address map
defines other system bus cycles that are forwarded to the AGP.