1. Intel
®
MAX
®
10 JTAG BST Overview
Intel
®
MAX
®
10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing
(BST).
When you perform BST, you can test pin connections without using physical test
probes and capture functional data during normal operation. The boundary-scan cells
(BSCs) in a device can force signals onto pins, or capture data from pins or core logic
signals. Forced test data is serially shifted in from the TDI pin to the BSCs. Captured
data is serially shifted out to the TDO pin for external comparison with expected
results.
Note: You can perform BST on Intel MAX 10 devices before, after, and during configuration.
Related Information
• Intel MAX 10 FPGA Configuration User Guide
Provides more information about JTAG in-system programming.
• IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices
Provides more information on IEEE 1149.1 JTAG boundary-scan testing.
• JTAG BST Architecture on page 4
• JTAG Boundary-Scan Register on page 5
• BST Operation Control on page 7
• I/O Voltage Support in the JTAG Chain on page 10
• Enabling and Disabling JTAG BST Circuitry on page 11
• Guidelines for JTAG BST on page 12
• Boundary-Scan Description Language Support on page 13
UG-M10JTAG | 2019.05.10
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