Intel MAX 10 JTAG User Manual

Figure 1. JTAG Circuitry Functional Model
• Test access port (TAP) controller—controls the JTAG BST.
•
TMS and TCK pins—operate the TAP controller.
•
TDI and TDO pins—provide the serial path for the data registers.
•
The TDI pin also provides data to the instruction register to generate the control logic for the data
registers.
a
UPDATEIR
CLOCKIR
SHIFTIR
UPDATEDR
CLOCKDR
SHIFTDR
TDI
Instruction Register
Bypass Register
Boundary-Scan Register
Instruction Decode
TMS
TCK
TAP
Controller
ISP Registers
TDO
Data Registers
Device ID Register
2.3. JTAG Boundary-Scan Register
You can use the boundary-scan register to test external pin connections or to capture
internal data. The boundary-scan register is a large serial shift register that uses the
TDI pin as an input and the TDO pin as an output. The boundary-scan register consists
of 3-bit peripheral elements that are associated with Intel MAX 10 I/O pins.
2.3.1. Boundary-Scan Cells in Intel MAX 10 I/O Pin
The Intel MAX 10 3-bit BSC contains the following registers:
•
Capture registers—connect to internal device data through OUTJ, OEJ, and
PIN_IN signals.
•
Update registers—connect to external data through PIN_OUT and PIN_OE signals.
2. JTAG BST Architecture
UG-M10JTAG | 2019.05.10
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10 JTAG Boundary-Scan Testing User Guide
5

Intel MAX 10 JTAG Specifications

General

Brand	Intel
Model	MAX 10 JTAG
Category	Microcontrollers
Language	English

Summary

Intel MAX 10 JTAG BST Overview

JTAG BST Architecture

JTAG Pins

Details the four JTAG interface pins (TDI, TDO, TMS, TCK) and their functions and characteristics.

JTAG Circuitry Functional Model

Explains the functional model of the JTAG BST circuitry, including required registers like Instruction, Bypass, and Boundary-Scan.

JTAG Boundary-Scan Register

Describes the boundary-scan register's role in testing pin connections and capturing internal data.

Boundary-Scan Cells in Intel MAX 10 I/O Pin

Details the 3-bit boundary-scan cells (BSCs) in Intel MAX 10 I/O pins, including capture and update registers.

BST Operation Control

JTAG IDCODE

Explains the unique IDCODE for identifying Intel MAX 10 devices within a JTAG chain.

JTAG Secure Mode

Describes JTAG secure mode, which restricts allowed JTAG instructions to SAMPLE/PRELOAD, BYPASS, EXTEST, and IDCODE.

JTAG Private Instruction

Warns against invoking specific instruction codes that can damage the device and render it unusable.

JTAG Instructions

Details various JTAG instructions like SAMPLE/PRELOAD, EXTEST, BYPASS, USERCODE, IDCODE, HIGHZ, CLAMP, USERO, and USER1.

I/O Voltage Support in the JTAG Chain

Enabling and Disabling JTAG BST Circuitry

Guidelines for JTAG BST

Boundary-Scan Description Language Support

Document Revision History