Hardware Specification
Version 1.4 3-3
Table 3-1. Memory Cacheability Map
Addresses
(in hex) Size Description
Shared by All
Processors? Cacheable? Comment
0000_0000h –
0009_FFFFh
640KB Main memory Yes Yes
000A_0000h –
000B_FFFFh
128KB Display buffer for
video adapters
Yes No
000C_0000h –
000D_FFFFh
128KB ROM BIOS for add-on
cards
Yes Yes
000E_0000h –
000F_FFFFh
128KB System ROM BIOS Yes Yes
0010_0000h –
0FEBF_FFFFh
Main memory Yes Yes Maximum address
depends on total memory
installed in the system.
Not specified. Memory-mapped I/O
devices
Yes
2
Not
specified
Top unused memory
0FEC0_0000h –
0FECF_FFFFh
1
APIC I/O unit Yes No Refer to the register
description in the APIC
data book.
0FED0_0000h –
0FEDF_FFFFh
Reserved for
memory-mapped I/O
devices
Yes
2
Not
specified
0FEE0_0000h-
0FEEF_FFFFh
1
APIC Local Unit No No Refer to the register
description in the APIC
data book.
0FEF0_0000h –
0FFFD_FFFFh
Reserved for
memory-mapped I/O
devices
Yes
2
Not
specified
0FFFE_0000h –
0FFFF_FFFFh
128KB Initialization ROM Yes Not
specified
NOTES:
1. These addresses are part of this specification. The other address regions in this table are shown for reference only, and
should not be construed as the sole definition of a PC/AT-compatible address space format or cache.
2. Any memory-mapped device should be shareable unless the nature of the device is that there is one device per
processor.
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