Intel MultiProcessor - Default Configuration for Discrete APIC

Default Configurations
Version 1.4 5-3
B
C
D
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
IRQ1
0
1
2
3
4
5
6
7
I/O
82489DX
APIC
MASTER
8259A PIC
SLAVE
8259A PIC
IRQ8#
14
15
14
15
8254 TIMER
9
10
11
9
10
11
IRQ3-7,
9-12,14,15
IRQ13
EISA DMA CHAINING
FERR#
IGNNE#
ICC BUS
INTR
FERR
SAMPLING
PRSTPNMI PINT
LINTIN0 LINTIN1
NMI RESET
NMI
RESET
INTR
LOCAL
82489DX APIC
CPU 1
NMI
INTR
PRSTPNMI PINT
LINTIN0 LINTIN1
LOCAL
82489DX APIC
NMI INTR
CPU 3
IMCR
I/O BUS
ExtINTA
INTA
TRAP
ExtINTA
INTA
TRAP
INTEL486
RESET
GLUE
INTEL486
E0
REG.
MARK
FROM BSP
INTA
BSP AP2
EDGE/LEVEL TRIGGER
POLARITY CONTROL
12
ABFULL
(PS/2 MOUSE)
LITM3-7,
9-12,14,15
LITMx
IRQx
ABFULL
SAMPLING
12
13
8
3
4
5
6
7
3
4
5
6
7
SHADED AREAS:
A: OPTIONAL IF VIRTUAL WIRE MODE IS IMPLEMENTED
B,C: MAY NOT BE EXTERNALIZED WITH SOME EISA CHIPSETS
C,D: EISA BUS SPECIFIC
Figure 5-1. Default Configuration for Discrete APIC