Intel MultiProcessor - System Memory Cacheability and Shareability; System Memory Address Map

MultiProcessor Specification
3-2 Version 1.4
SYSTEM-BASED
MEMORY
VIDEO BUFFER
ROM EXTENSIONS
EXPANSION ROM
SHADOWED
EXPANSION BIOS
SHADOWED BIOS
EXTENDED
MEMORY REGION
I/O APIC
LOCAL APIC
BIOS PROM
0000_0000H
000A_0000H
000C_0000H
000D_0000H
000E_0000H
000F_0000H
0010_0000H
FEC0_0000H
FED0_0000H
FEE0_0000H
FEF0_0000H
FFFE_0000H
FFFF_FFFFH
640K
1MB
4GB
MEMORY-MAPPED
I/O SPACE
PART OF THIS SPECIFICATION
UNSHADED ADDRESS REGIONS ARE FOR REFERENCE ONLY AND SHOULD NOT BE CONSTRUED AS THE SOLE
DEFINITION OF A PC/AT-COMPATIBLE ADDRESS SPACE.
Figure 3-1. System Memory Address Map
3.2 System Memory Cacheability and Shareability
The cacheability and shareability of the physical memory space are defined in Table 3-1. The
address space reserved for the local APIC is used by each processor to access its own local APIC.
The address space reserved for the I/O APIC must be shareable by all processors to permit dynamic
reconfiguration.