Intel MultiProcessor - Page 6

Contents
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3.6.6 APIC Identification ..................................................................... 3-13
3.6.7 APIC Interval Timers.................................................................. 3-13
3.6.8 Multiple I/O APIC Configurations ............................................... 3-13
3.7 RESET Support ...................................................................................... 3-14
3.7.1 System-wide RESET .................................................................3-14
3.7.2 System-wide INIT....................................................................... 3-15
3.7.3 Processor-specific INIT.............................................................. 3-15
3.8 System Initial State................................................................................. 3-16
3.9 Support for Fault-resilient Booting .......................................................... 3-16
Chapter 4 MP Configuration Table
4.1 MP Floating Pointer Structure................................................................... 4-3
4.2 MP Configuration Table Header ............................................................... 4-5
4.3 Base MP Configuration Table Entries....................................................... 4-6
4.3.1 Processor Entries......................................................................... 4-7
4.3.2 Bus Entries................................................................................. 4-10
4.3.3 I/O APIC Entries......................................................................... 4-12
4.3.4 I/O Interrupt Assignment Entries................................................ 4-12
4.3.5 Local Interrupt Assignment Entries............................................ 4-15
4.4 Extended MP Configuration Table Entries.............................................. 4-17
4.4.1 System Address Space Mapping Entries................................... 4-18
4.4.2 Bus Hierarchy Descriptor Entries............................................... 4-21
4.4.3 Compatibility Bus Address Space Modifier Entries.................... 4-22
Chapter 5 Default Configurations
5.1 Discrete APIC Configurations................................................................... 5-2
5.2 Integrated APIC Configurations................................................................ 5-4
5.3 Assignment Of I/O Interrupts To The APIC I/O Unit ................................. 5-6
5.3.1 EISA and IRQ13 .......................................................................... 5-7
5.3.2 Level-triggered Interrupt Support................................................. 5-7
5.4 Assignment Of System Interrupts To The APIC Local Unit ...................... 5-7