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SE7520JR2
Intel SE7520JR2 Technical Manual
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Platform Management
Intel® Server Board SE7520JR2
Revision 1.0
C78844-002
146
Sensor Name
Sensor
Number
Sensor Type
Event /
Reading
Type
Event Offset
Triggers
A
ssert /
Deassert
Readable
Value /
Offsets
EventData
Rearm
Standby
System Event
83h
System Event
12h
Sensor
Specific
6Fh
OEM System Boot
Event (Hard
Reset)
PEF Action
As –
Trig
Offset
A
–
Button 84h
Button
14h
Sensor
Specific
6Fh
Power Button
Sleep Button
Reset Button
As –
Trig
Offset
A
X
SMI Timeout
85h
SMI Timeout
F3h
Digital
Discrete
03h
State Asserted
State Deasserted
As –
Trig
Offset
A
–
Sensor Failure
86h
Sensor Failure
F6h
OEM
Sensor
Specific
73h
I2C device not
found
I2C device error
detected
I2C Bus Timeout
As –
Trig
Offset
A
X
NMI Signal State
87h
OEM
C0h
Digital
Discrete
03h
State Asserted
State Deasserted
– –
–
–
–
SMI Signal State
88h
OEM
C0h
Digital
Discrete
03h
State Asserted
State Deasserted
– –
–
–
–
DIMM Sparing
Redundancy
89h
Availability Status
0Bh
Discrete
0Bh
Fully Redundant
Non-red:Suff res
from redund
Non-red:Suff res
from insuff res
Non-red:Insuff res
As –
Trig
Offset
A
–
DIMM Sparing
Enabled
8Ah
Entity Presence
25h
Sensor
Specific
6Fh
Entity Present
As
–
T
rig Offset
A
–
Memory Mirroring
Redundancy
8Bh
Availability Status
0Bh
Discrete
0Bh
Fully Redundant
Non-red:Suff res
from redund
Non-red:Suff res
from insuff res
Non-red:Insuff res
As –
Trig
Offset
A
–
Memory Mirroring
Enabled
8Ch
Entity Presence
25h
Sensor
Specific
6Fh
Entity Present
As
–
T
rig Offset
A
–
Processor 1
Status
90h
Processor
07h
Sensor
Specific
6Fh
IERR
Thermal Trip
FRB1, FRB2,
FRB3
Config Error
Presence
Disabled
As & De
–
Trig Offset
M
X
145
147
Table of Contents
Default Chapter
4
Table of Contents
4
1 Introduction
19
Chapter Outline
19
Server Board Use Disclaimer
20
2 Server Board Overview
21
Server Board SE7520JR2 SKU Availability
21
Server Board SE7520JR2 Feature Set
21
Figure 1. SE7520JR2 Board Layout
23
Table 1: Baseboard Layout Reference
24
Figure 2. Server Board Dimensions
25
3 Functional Architecture
26
Figure 3. Server Board SE7520JR2 Block Diagram
26
Processor Sub-System
27
Processor Voltage Regulators
27
Reset Configuration Logic
27
Processor Module Presence Detection
27
Gtl2006
27
Common Enabling Kit (CEK) Design Support
28
Processor Support
28
Figure 4. CEK Processor Mounting
28
Table 2: Processor Support Matrix
28
Jumperless Processor Speed Settings
29
Mixed Processor Cache Sizes
29
Mixed Processor Families
29
Mixed Processor Models
29
Mixed Processor Steppings
29
Processor Mis-Population Detection
29
EM64T Technology Support
30
Hyper-Threading Technology
30
Intel® Speedstep® Technology
30
Microcode
30
Processor Cache
30
Multiple Processor Initialization
30
CPU Thermal Sensors
31
Processor Thermal Control Sensor
31
Processor Thermal Trip Shutdown
31
Processor IERR
31
Intel® E7520 Chipset
31
Memory Controller Hub (MCH)
32
Front Side Bus (FSB)
32
MCH Memory Sub-System Overview
32
PCI Express
32
Hub Interface
33
PCI-X Hub (PXH)
33
Full-Height Riser Slot
33
Low Profile Riser Slot
33
I/Oxapic Controller
34
Smbus Interface
34
I/O Controller Hub (ICH5-R)
34
PCI Interface
34
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
34
SATA Controller
35
Low Pin Count (LPC) Interface
35
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
35
Universal Serial Bus (USB) Controller
36
Rtc
36
General Purpose I/O (GPIO)
36
Enhanced Power Management
36
System Management Bus (Smbus 2.0)
36
Memory Sub-System
37
Memory Sizing
37
Memory Population
38
Figure 5. Identifying Banks of Memory
38
Table 3: Supported DDR-266 DIMM Populations
39
Table 4: Supported DDR-333 DIMM Populations
39
ECC Memory Initialization
40
Memory Test
40
Table 5: Supported DDR2-400 DIMM Populations
40
Memory Monitoring
41
Table 6: Memory Monitoring Support by Server Management Level
41
Memory RASUM Features
42
DRAM ECC - Intel® X4 Single Device Data Correction (X4 SDDC)
42
Integrated Memory Scrub Engine
42
Retry on Uncorrectable Error
43
Integrated Memory Initialization Engine
43
DIMM Sparing Function
44
Memory Mirroring
45
Figure 6. Four DIMM Memory Mirror Configuration
45
Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only)
46
Logging Memory RAS Information to the SEL
47
I/O Sub-System
47
PCI Subsystem
47
P32-A: 32-Bit, 33-Mhz PCI Subsystem
48
P64-A and P64-B: 64-Bit, 100Mhz PCI Subsystem
48
P64-Express: Dual X4 PCI Bus Segment
48
PCI Riser Slots
48
Table 7: PCI Bus Segment Characteristics
48
PCI Scan Order
49
PCI Bus Numbering
49
Device Number and IDSEL Mapping
50
Table 8: PCI Configuration Ids and Device Numbers
51
Resource Assignment
52
Automatic IRQ Assignment
52
Option ROM Support
52
PCI Apis
52
Split Option ROM
52
Interrupt Routing
52
Legacy Interrupt Routing
52
APIC Interrupt Routing
53
Table 9: PCI Interrupt Routing/Sharing
53
Legacy Interrupt Sources
54
Serialized IRQ Support
54
Table 10: Interrupt Definitions
54
IRQ Scan for PCIIRQ
55
Figure 8. Interrupt Routing Diagram (ICH5-R Internal)
55
Figure 9. Interrupt Routing Diagram
56
Figure 10. PCI Interrupt Mapping Diagram
57
Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card
57
SCSI Support
58
LSI* 53C1030 Dual Channel Ultra320 SCSI Controller
58
Zero Channel RAID
60
IDE Support
60
Ultra ATA/100
61
IDE Initialization
61
SATA Support
61
Sata Raid
62
Intel® RAID Technology Option ROM
62
Video Support
62
Video Modes
62
Video Memory Interface
63
Table 11: Video Modes
63
Table 12: Video Memory Interface
63
Dual Video
64
Network Interface Controller (NIC)
64
NIC Connector and Status Leds
65
USB 2.0 Support
65
Super I/O Chip
65
Gpios
65
Table 13: Super I/O GPIO Usage Table
65
Serial Ports
67
Table 14: Serial a Header Pin-Out
67
Figure 12. Serial Port Mux Logic
68
Figure 13. RJ45 Serial B Port Jumper Block Location and Setting
68
Removable Media Drives
69
Floppy Disk Support
69
Keyboard and Mouse Support
69
Wake-Up Control
69
BIOS Flash
69
Configuration and Initialization
70
Memory Space
70
Figure 14. Intel ® Xeon™ Processor Memory Address Space
70
DOS Compatibility Region
71
Figure 15. DOS Compatibility Region
71
Extended Memory
73
Figure 16. Extended Memory Map
73
Memory Shadowing
74
System Management Mode Handling
75
Table 15: SMM Space Table
75
I/O Map
76
Table 16: I/O Map
76
Accessing Configuration Space
78
CONFIG_ADDRESS Register
79
Clock Generation and Distribution
79
4 System BIOS
80
BIOS Identification String
80
Figure 17. BIOS Identification String
80
Flash Architecture and Flash Update Utility
81
BIOS Power on Self Test (POST)
81
User Interface
81
System Activity Window
82
Splash Screen/Diagnostic Window
82
Figure 18. POST Console Interface
82
POST Activity Window
83
BIOS Boot Popup Menu
83
BIOS Setup Utility
84
Localization
84
Table 17: Sample BIOS Popup Menu
84
Table 18: BIOS Setup Keyboard Command Bar Options
84
Entering BIOS Setup
85
Main Menu
85
Table 19: BIOS Setup, Main Menu Options
85
Advanced Menu
86
Table 20: BIOS Setup, Advanced Menu Options
86
Table 21: BIOS Setup, Processor Configuration Sub-Menu Options
87
Table 22: BIOS Setup IDE Configuration Menu Options
88
Table 23: Mixed P-ATA-S-ATA Configuration with Only Primary P-ATA
89
Table 24: BIOS Setup, IDE Device Configuration Sub-Menu Selections
90
Table 25: BIOS Setup, Floppy Configuration Sub-Menu Selections
91
Table 26: BIOS Setup, Super I/O Configuration Sub-Menu
91
Table 27: BIOS Setup, USB Configuration Sub-Menu Selections
92
Table 28: BIOS Setup, USB Mass Storage Device Configuration Sub-Menu Selections
92
Table 29: BIOS Setup, PCI Configuration Sub-Menu Selections
93
Table 30: BIOS Setup, Memory Configuration Sub-Menu Selections
94
Boot Menu
95
Table 31: BIOS Setup, Boot Menu Selections
95
Table 32: BIOS Setup, Boot Settings Configuration Sub-Menu Selections
96
Table 33: BIOS Setup, Boot Device Priority Sub-Menu Selections
97
Table 34: BIOS Setup, Hard Disk Drive Sub-Menu Selections
97
Table 35: BIOS Setup, Removable Drives Sub-Menu Selections
97
Table 36: BIOS Setup, CD/DVD Drives Sub-Menu Selections
97
Security Menu
98
Table 37: BIOS Setup, Security Menu Options
98
Server Menu
99
Table 38: BIOS Setup, Server Menu Selections
99
Table 39: BIOS Setup, System Management Sub-Menu Selections
100
Table 40: BIOS Setup, Serial Console Features Sub-Menu Selections
101
Table 41: BIOS Setup, Event Log Configuration Sub-Menu Selections
101
Exit Menu
102
Rolling BIOS and On-Line Updates
102
Table 42: BIOS Setup, Exit Menu Selections
102
Flash Update Utility
103
Flash BIOS
103
User Binary Area
103
Recovery Mode
103
BIOS Recovery
104
Configuration Reset
104
OEM Binary
105
Security
105
Operating Model
106
Table 43: Security Features Operating Model
106
Password Clear Jumper
108
Extensible Firmware Interface (EFI)
108
EFI Shell
108
Operating System Boot, Sleep, and Wake
108
Microsoft* Windows* Compatibility
108
Advanced Configuration and Power Interface (ACPI)
109
Sleep and Wake Functionality
109
Power Switch off to on
110
On to off (os Absent)
110
On to off (os Present)
110
On to Sleep (ACPI)
110
Sleep to on (ACPI)
111
System Sleep States
111
Table 44: Supported Wake Events
111
4.10 PXE BIOS Support
112
4.11 Console Redirection
112
5 Platform Management
113
Table 45: Suppoted Management Features by Tier
113
Platform Management Architecture Overview
115
Figure 19. On-Board Platform Management Architecture
115
IPMI Messaging, Commands, and Abstractions XXX
116
Standby
116
IPMI 'Sensor Model
117
Management Controllers
118
Private Management Busses
118
On-Board Platform Management Features and Functionality
121
Figure 20. Mbmc in a Server Management System
121
External Interface to the Mbmc
122
Power Control Interfaces
122
Server Management I C Buses
122
Table 46: Server Management I 2 C Bus ID Assignments
122
Mbmc Hardware Architecture
123
Figure 21. External Interfaces to Mbmc
123
Figure 22. Mbmc Block Diagram
124
Power Supply Interface Signals
124
Figure 23. Power Supply Control Signals
125
Power Control Sources
126
Power-Down Sequence
126
Power-Up Sequence
126
System Reset Control
126
Reset Signal Output
126
Table 47: Power Control Initiators
126
Reset Control Sources
127
Control Panel System Reset
127
Table 48: System Reset Sources and Actions
127
Control Panel Indicators
128
Table 49: SSI Power LED Operation
128
Control Panel Inputs
129
Table 50: Fault / Status LED
129
Table 51: Chassis ID LED
129
Baseboard Fan Control
131
Mbmc Peripheral Smbus
131
Secure Mode Operation
131
System Event Log (SEL)
131
SEL Erasure
132
Timestamp Clock
132
Watchdog Timer
131
Sensor Data Record (SDR) Repository
132
Initialization Agent
132
Event Message Reception
133
Field Replaceable Unit (FRU) Inventory Devices
133
Mbmc FRU Inventory Area Format
133
NMI Generation
133
SMI Generation
133
Mbmc Self Test
134
Messaging Interfaces
134
Channel Management
134
User Model
134
Request/Response Protocol
134
Host to Mbmc Communication Interface
134
Table 52: Suported Channel Assignments
134
LAN Interface
135
Table 53: LAN Channel Capacity
135
Event Filtering and Alerting
136
Platform Event Filtering (PEF)
136
Alert over LAN
137
Mbmc Sensor Support
137
Table 54: PEF Action Priorities
137
Table 55: Platform Sensors for On-Board Platform Instrumentation
138
IMM BMC Sensor Support
142
Table 56. Platform Sensors for Intel Management Modules - Professional and Advanced
142
System Management BIOS (SMBIOS)
148
Vital Product Data (VPD)
148
Wired for Management (WFM)
148
6 Error Reporting and Handling
149
Fault Resilient Booting (FRB)
149
FRB1 - BSP Self-Test Failures
149
FRB2 - BSP POST Failures
149
FRB3 - BSP Reset Failures
150
AP Failures
151
Treatment of Failed Processors
151
Memory Error Handling in RAS Mode
152
Memory Error Handling in Non-RAS Mode
153
Table 57: Memory Error Handling Mbmc Vs Sahalee
153
DIMM Enabling
154
Single-Bit ECC Error Throttling Prevention
154
Table 58: Memory Error Handling in Non-RAS Mode
154
Error Logging
155
PCI Bus Error
155
Processor Bus Error
155
Memory Bus Error
156
System Limit Error
156
Processor Failure
156
Boot Event
156
Error Messages and Error Codes
156
POST Error Messages
156
Table 59: Memory BIOS Messages
156
Table 60: Boot BIOS Messages
157
Table 61: Storage Device BIOS Messages
157
Table 62: Virus Related BIOS Messages
160
Table 63: System Configuration BIOS Messages
160
Table 64: CMOS BIOS Messages
161
Table 65: Miscellaneous BIOS Messages
161
Table 66: USB BIOS Error Messages
161
POST Error Codes
162
Table 67: SMBIOS BIOS Error Messages
162
Table 68: Error Codes and Messages
162
Table 69: Error Codes Sent to the Management Module
164
BIOS Generated POST Error Beep Codes
165
Table 70: BIOS Generated Beep Codes
165
Boot Block Error Beep Codes
166
BMC Generated Beep Codes (Professional/Advanced Only)
166
Table 71: Troubleshooting BIOS Beep Codes
166
Table 72: Boot Block Error Beep Codes
166
Checkpoints
167
System ROM BIOS POST Task Test Point (Port 80H Code)
167
Diagnostic Leds
167
Table 73: BMC Beep Code
167
Table 74: POST Progress Code LED Example
167
POST Code Checkpoints
168
Figure 24. Location of Diagnostic Leds on Baseboard
168
Table 75: POST Code Checkpoints
168
Bootblock Initialization Code Checkpoints
170
Table 76: Bootblock Initialization Code Checkpoints
170
Bootblock Recovery Code Checkpoint
171
Table 77: Bootblock Recovery Code Checkpoint
171
DIM Code Checkpoints
172
Table 78: DIM Code Checkpoints
172
ACPI Runtime Checkpoints
173
POST Progress FIFO (Professional / Advanced Only)
173
Memory Error Codes
173
Table 79: ACPI Runtime Checkpoints
173
Table 80: Memory Error Codes
173
Light Guided Diagnostics
174
7 Connectors and Jumper Blocks
175
Power Connectors
175
Table 81: Power Connector Pin-Out
175
Table 82: 12V Power Connector (J4J1)
175
Riser Slots
176
Low Profile PCI-X Riser Slot
176
Table 83: Power Supply Signal Connector (J1G1)
176
Table 84: IDE Power Connector Pinout (U2E1)
176
Table 85: Low Profile Riser Slot Pinout
176
Full Height PCI-X Riser Slot
179
Table 86: Full-Height Riser Slot Pinout
180
System Management Headers
184
Intel® Management Module Connector
184
Table 87: IMM Connector Pinout (J1C1)
184
ICMB Header
187
IPMB Header
187
Table 88: ICMB Header Pin-Out (J1D1)
187
Table 89: IPMB Connector Pin-Out (J3F1)
188
OEM RMC Connector (J3B2)
189
Control Panel Connectors
189
Table 90: OEM RMC Connector Pinout (J3B2)
189
Table 91: 100-Pin Flex Cable Connector Pin-Out (for Intel Chassis W/Backplane) (J2J1)
189
Table 92: 50-Pin Control Panel Connector (Intel Chassis W/No Backplane) (J1J2)
190
Table 93: Control Panel SSI Standard 34-Pin Header Pin-Out
191
I/O Connectors
192
VGA Connector
192
Figure 25. 34-Pin SSI Compliant Control Panel Header
192
Table 94: VGA Connector Pin-Out
192
NIC Connectors
193
SCSI Connectors
193
Table 95: RJ-45 10/100/1000 NIC Connector Pin-Out
193
Table 96: Internal/External 68-Pin VHDCI SCSI Connector Pin-Out
193
Connector
194
Table 97: ATA-100 40-Pin Connector Pin-Out (J3K1)
194
SATA Connectors
195
Floppy Controller Connector
195
Table 98: SATA Connector Pin-Out (J1H1 and J1H5)
195
Serial Port Connectors
196
Table 99: Legacy 34-Pin Floppy Drive Connector Pin-Out (J3K2)
196
Table 100: External RJ-45 Serial B Port Pin-Out
196
Table 101: Internal 9-Pin Serial a Header Pin-Out (J1A3)
196
Keyboard and Mouse Connector
197
USB Connector
197
Table 102: Stacked PS/2 Keyboard and Mouse Port Pin-Out
197
Table 103: External USB Connector Pin-Out
197
Fan Headers
198
Table 104: Internal 1X10 USB Connector Pin-Out (J1F1)
198
Table 105: Internal 2X5 USB Connector (J1G1)
198
Table 106: CPU1/CPU2 Fan Connector Pin-Out (J5F2, J7F1)
199
Table 107: Intel Server Chassis Fan Header Pin-Out (J3K6)
199
Misc. Headers and Connectors
200
Chassis Intrusion Header
200
Hard Drive Activity LED Header
200
Table 108: 3-Pin Fan Speed Controlled Fan Header (J3K3)
200
Table 109: Chassis Intrusion Header (J1A1)
200
Table 110: Hard Drive Activity LED Header(J1A2)
200
Jumper Blocks
201
Figure 26. System Configuration (J1H2) Jumper Block Settings
201
Table 111: Jumper Block Definitions
201
8 Design and Environmental Specifications
202
Server Board SE7520JR2 Design Specification
202
Power Supply Requirements
202
Output Connectors
202
Table 112: Board Design Specifications
202
Figure 27. Power Harness Specification Drawing
203
Table 113: P1 Main Power Connector
204
Table 114: P2 Processor Power Connector
204
Grounding
205
Table 115: P3 Baseboard Signal Connector
205
Table 116: Peripheral Power Connectors
205
Table 117: P7 Hard Drive Power Connector
205
Remote Sense
206
Standby Outputs
206
Voltage Regulation
207
Dynamic Loading
207
Table 118: Voltage Regulation Limits
207
Table 119: Transient Load Requirements
207
Capacitive Loading
208
Closed Loop Stability
208
Common Mode Noise
208
Ripple / Noise
208
Table 120: Capacitve Loading Conditions
208
Table 121: Ripple and Noise
208
Soft Starting
209
Zero Load Stability Requirements
209
Timing Requirements
209
Table 122: Output Voltage Timing
209
Figure 28. Output Voltage Timing
210
Table 123: Turn On/Off Timing
210
Residual Voltage Immunity in Standby Mode
211
Figure 29. Turn On/Off Timing (Power Supply Signals)
211
Product Regulatory Compliance
212
Product Safety Compliance
212
Product EMC Compliance - Class a Compliance
212
Certifications / Registrations / Declarations
213
Product Regulatory Compliance Markings
213
Table 124: Product Certification Markings
213
Electromagnetic Compatibility Notices
214
Fcc (Usa)
214
Industry Canada (ICES-003)
214
Europe (CE Declaration of Conformity)
215
Taiwan Declaration of Conformity (BSMI)
215
Korean Compliance (RRL)
215
9 Miscellaneous Board Information
216
Updating the System Software
216
Programming FRU and SDR Data
216
Clearing CMOS
217
CMOS Clear Using J1H2 Jumper Block
217
CMOS Clear Using Control Panel
217
BIOS Recovery Operation
218
Appendix A: Integration and Usage Tips
221
Glossary
222
Reference Documents
225
Other manuals for Intel SE7520JR2
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Intel SE7520JR2 Specifications
General
Brand
Intel
Model
SE7520JR2
Category
Computer Hardware
Language
English
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