Jäger ADwin - Annex; A.1 List of Abbreviations

ADwin Installation, manual version 2.1, December 2005 A-1
Annex
ADwin
Annex
A.1 List of Abbreviations
A.2
A/D A
na
l
og
t
o
Di
g
it
a
l
A
DC Analog to Digital Converter
A
DSP Analog Devices Signal Pro-
cessor
b Binary number
CLK CLocK
CLR CLeaR
CMOS Complementary Metal Oxide
Semiconductor
CMRR Common Mode Rejection
Ratio
D/A Digital to Analog
DAC Digital to Analog Converter
DIL Dual InLine
DIO Digital Input / Output
DIR DIRection
DMA Direct Memory Access
DMM Digital Multi-Meter
DNL Differential Non-Linearity
DRAM Dynamic Random Access
Memory
DSP Digital Signal Processor
EOC End Of Conversion
EMC Electro-Magnectic Compati-
bility
ESD Electro-Static Discharge
FPGA Field Programmable Gate
Array
FSR Full Scale Range
GND GrouND
h
/
H
ex
H
exa
d
ec
i
ma
l
num
b
er
I/O Input / Output
IC Integrated Circuit
InAmp Instrumentation Amplifier
INL Integral Non-Linearity
IRQ Interrupt ReQuest
kB kilo Byte (= 1024 Byte)
kByte seekB
LED Light Emitting Diode
LSB Least Significant bit
MB Mega-Byte (= 1024kB)
MByte seeMB
MSB Most Significant bit
MUX Multiplexer
OpAmp Operational Amplifier
PC Personal Computer
PGA Programmable Gain Ampli-
fier
S&H Sample & Hold
SRAM Static Random Access Mem-
ory
TTL Transistor-Transistor Logic
V
cc
Voltage collector-collector
V
ee
Voltage emitter-emitter
M
anu
f
ac
t
urer
A
D Analog Devices
BB Burr-Brown
LT Linear Technology
TI Texas Instruments