JBL JSR-400 - Circuit Description

13
Dolby Pro-Logic
Ò
A/V Receiver JSR-400
CIRCUIT DESCRIPTION
1. Surround Circuits
This model incorporates a surround processor circuit.
Fig. 1 is a block diagram of the surround processor circuit. The microprocessor transfers the data to the Dolby Pro-Logic
decoder and Time Delay Device to operate the circuits in each mode.
1) BYPASS
Set to this mode to listen to ordinary stereo sound. The rear L/R and center outputs will be muted.
Input
Auto-
balance
Control
X1
X1
IC10
NJW1102
AMP
AMP
C
S
C
S
electric
vol.
Center/
Operating
Mode
Control
Adaptive
Matrix
By-Pass Line
L
R
C
S
S
S
V LR V CS
IC11
NJU9702
Time
Delay
7knz
LPF
Modified
Dolby B NR
Noise
Generator
Noise
Sequencer
IC5
LC4966
Buffer
Buffer
L Input
R Input
MASTER
VOLUME
TONE
CONTROL
TONE
CONTROL
L
C
R
S
AMP
AMP
AMP
AMP
SPEAKER
FRONT L
CENTER
FRONT L
SURROUND L
SURROUND L
Fig. 1
Block diagram of the surround
processor circuit
SURROUND
SURROUND
IC5
OUTPUT
OUTPUT
SOURCE
SOURCE
L
R
LC4966
Fig. 2