L3 FA5000 - Table 205. Main Processor Troubleshooting Chart

COMPONENT MAINTENANCE MANUAL
AVIATION RECORDERS
Model FA5000
Rev. 03 Page 223
Feb. 27/13
FDR Function Testing & Fault Isolation
23–70−40
Use or disclosure of information on this sheet is subject to
the restrictions on the cover page of this document.
Table 205. Main Processor Troubleshooting Chart
Item
ID
Function Type Failure
Mode
Local Effect Next Effect End Effect
A001
− DSP
Watch Dog Timer;
ARINC 429 RX/TX; Dis-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Over/Under
Voltage
The DSP fails:
No program
execution or
storage;
FPGA, all re-
gisters and all
interfaces fail
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Dis-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Incorrect O/P The DSP fails:
No program
execution or
storage;
FPGA, all re-
gisters and all
interfaces fail
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Dis-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Single Event
Upset (SEU)
The DSP ini-
tially does not
operate
The MP PWA
initially does
not operate
The CVDR initially does not
operate: some data may be
corrupt, lost and/or may not be
recorded, stored or copied
NOTE: After the Watch Dog
Timer has timed out, it forces
the system to reset
A002 −
FPGA
Watch Dog Timer;
ARINC 429 RX/TX; Dis-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Over/Under
Voltage
The FPGA
fails: The sys-
tem is unable
to reboot
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Dis-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Incorrect O/P The FPGA
fails: The sys-
tem is unable
to reboot
The MP PWA
fails to operate
The CVDR fails to operate
Rev.04 Page 223
Mar. 21/14
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