LeCroy WAVERUNNER 6000 SERIES - Page 29

4.6.1.1 JTAG Chains
Control
FPGA
EN
B
MAM2
TDI TDO
MAM1
TDO TDI
MAD
TDO TDI
MAM3
TDI TDO
TCK TMSTCK TMS
TRS TTRST
TCK TMS TCK TMS
TRST TRST
Channel 1-2
Channel 3-4
MAD
TDI TDO
MAM1
TDI TDO
TCK TMSTCK TMS
TRSTTRST
MAM3
TDO TDI
MAM2
TDO TDI
TCK TMS TCK TMS
TRS T TRST
ATC
(MTT)
TDO TDI
TCK TMS
EN
B
EN
B
JTAG
Control
EN
B
EN
B
EN
B
TDI
_TB
TMS
_TB
TCK
_TB
TDI
_CH
TMS
_CH
TCK
_CH
TDO_CH
TDO_TB
Dashed arrows show "NORES" connections when
Channels 3 & 4 are unpopulated
TRST
_CH
8 bit IR
18bit DR
3 bit IR
21 bit DR
3 bit IR
21 bit DR
3 bit IR
21 bit DR
5(8) bit IR
18(15-145) bit DR
Figure 4-4 JTGA Device Chains
The software detects the devices on JTAG chain at startup
4.6.1.2 Serial chains
Control
FPGA
SPI Interface:
MFE Relay Reg
SCAN SCLK LD
Channel 1
Ext Trig
LD SCLK
8 bit16 bit
MFE Relay Reg
8 bit16 bit
Dual DAC
32 bit
LD SCLK
SCLK LD
NCO
40 bit
SCLK LD
Octal DAC
16 bit
SCLK LD
SCAN SCLK LD
MFE Relay Reg
SCAN SCLK LD LD SCLK
8 bit16 bit
Dual DAC
32 bit
SCLK LD
Channel 2
MFE Relay Reg
SCAN SCLK LD
Channel 3
LD SCLK
8 bit16 bit
Dual DAC
32 bit
SCLK LD
MFE Relay Reg
SCAN SCLK LD LD SCLK
8 bit16 bit
Dual DAC
32 bit
SCLK LD
Channel 4
Dashed arrows
show "NORES"
connections when
Channels 3 & 4
are unpopulated
Figure 4-5 Serial Bus Device Chains
Theory of Operation 4-7