4-12 Theory of Operation
4.6.2.1.4 Control – The operating mode of the ADC is controlled
through JTAG, the control of each acquisition, start, stop etc
is controlled by the HTB.
4.6.2.2 MAM439 - 8 Megabytes DRAM
4.6.2.2.1 Signal I/O – The MAM439 has two, nine bit differential
inputs, each with two differential quadrature clock inputs.
Output is through an 8B/10B Ethernet transceiver.
4.6.2.2.2 Control – The state of MAM is controlled through JTAG and
through the Gigabit Ethernet link, the control of each
acquisition, clock, reset, stop etc is controlled by the HTB.
4.6.2.2.3 Decimation – When the sample rate is below 10GS/s, the
MAM439 ignores or decimates the correct amount of
samples so that the desired sample rate is achieved. The
ADC always digitizes at 10 GSs.
4.6.2.3 8b/10b Bus
ADC
MAM
MAM MAM
Control
FPGA
MTB
MST
ADC
MAM
MAMMAM
Buffer
Resistor
Jumper
8B 10B Bus
ATC
Figure 4-8 8b/10b Path
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