LG 65UB930T Service Manual

H13 Block Diagram (Internal)
DIF
TS (P)
System
Gl b l B b d
H13A H13D
Video Decoder
Mlti
STD
TS(P) TS(P)
GBB AFE
DVB-CI/CI+
Analog Chip Total Pin : 183w/o Power
Digital Chip Total Pin : 491w/o Power
AtoDPin : 79
TS(S)
GPU Ro
g
ue Han
USB2.0x3
TS(S)
SDRAM
(MCP)
Tuner
TS
(P)
Demux
Audio DSP
Multi-STD
Audio Decoder
LX4 HiFi EP
SIF
Gl
o
b
a
l
B
ase
b
an
d
V/Q, DVB-T/C ISDB-T
AAD
(THAT)
Mux
I2S(External)
M
u
lti
-
STD
HD Decoder
(Boda950)
Audio
2D GFX
JPG/PNG Decoder
JPG Encoder
UARTx3
EMAC
SCI
SPIx2
I2C 10
PHY
1ch@30MHz
w/ PLL
BTSC AFE
10b@18.432MHz
w/ PLL
Video Encoder
1080
p@
30f
p
s
g
GPIOx136
Audio L/R(4-
ch)
SCART out
SW
Audio DAC (48KHz)
Line Out
TrustZone
CPU
ARMCA9 Core
Dual 1.2GHz
Sound DSP
Clear Voice II
Perceptual
Volume Control
I2S
CPU
64KB SRAM
48KB ROM
I2C
x
10
eMMC
DMAC(8ch)
Timer
WDT
1ch L/R
Audio-ADC
24b@48KHz
p@ p
USB3.0 x1
Secure Engine
Audio DAC
(48KHz )
I2S
I2S
SW
CVBS(3ch)
CVBS
32KBI$
32KBD$
1MB L2 $
Volume
Control
Slim SPK
DivX
Bluetooth
Digital AMP
I2S(HPD)
SPDIF
UART
OTP
Timer
WDT
SRAM 16KB
Digital
Audio
Output
CVBS DAC
5x1ch (1ch)
Component(2ch)
CVBS AFE(2-ch)
12b@54MHz
CVBS-Out
Mux
10x3ch
DE
Encoder
LVDS
Tx
Mux
R
r
lacer
Scaler
D
R
SWSW
3ch Video
AFE
10b@148.5MHz
LVDS
Rx
CVD
Y/C
CVBS
BE
D
C
E
1
D
D
rmatter
O
N
MCU
Capture
Block
CVBS
DAC
Mux
E
PI/LVDS Combo
(120Hz)
MCU
HDMI-Rx 1.4
(
1-
p
ort PHY
)
DDR3 Controller
Tx
Audio PLL
w/ DCO
Source
TN
R
De-inte
r
Main/Sub
H3
D
VC
R
w/ LLPLL
Rx
I2Cx1
H3
D
DDR3 Controller
SPLL DPLL
FR
C
SR
E
PE
1
OS
D
LE
D
Output fo
TC
O
(3CH)
I2Cx1
HDMI
(1-Link)
HDMI
Vx1/
E
CPLL
DCO
x2
GPIOIx16
(
p)
3D, ARC, 4kx2k
DDR3 PHY
DDR3
Controller
DDR3 PHY
DDR3
Controller
DDR
PLL
DDR
PLL
16
8
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only

LG 65UB930T Specifications

General

Brand	LG
Model	65UB930T
Category	LED TV
Language	English