LG 65UB930T Service Manual

D14 Block Diagram (Internal)
Analog IP
Serial Flash
2.5V
(AIP)
LDO
3.3V
(I/O)
LDO
1.1V
(Core)
LDO
1.5V
(DDR3)
LDO
Added : D13Æ D14
Deleted : D13 Æ D14
CPU B I t f (PL301)
SPI I2C
Boot
ROM
SRAM ADO MCU0 MCU1 DMA
WDT
UART0 UART1
GPIO
I2C
MCURC
VD2
VD1
VD3
HEVC1
HDMI
PHY
1920x2160@60p
CPU
B
us
I
n
t
er
f
ace
(PL301)
H.264
Cre1
VD0
TE
PDEC
HEVC1
VDO VCP
HDMI
Link
PHY
ADO
H.264
(On2)
FHD
HDMI
1920x2160@60p
Serial/Parallel
TP Stream
HEVC2
C
o
re1
H.264
Core2
Bus Architecture
TE
PDEC
FHD
PHY
Memory Bus Interface (PL301)
CortexM3
SDRAM
lgm_top
DDR3 PHY (x16)
DDR3 PHY (x32)
DDR3PLL
SSPLL
DCO
DISPLL
lgm_top
Cl k/R t G
XTAL
(24.75MHz)
DDR3
-
1600
DDR3-1600
1Gbit
x32x32
Cl
oc
k/R
ese
t
G
en
DDR3
-
1600
DDR3-1600
1Gbit
DDR3
1600
1Gbit
1Gbit
DDR3
1600
1Gbit
1Gbit
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Only for training and service purposes
LGE Internal Use Only

LG 65UB930T Specifications

General

Brand	LG
Model	65UB930T
Category	LED TV
Language	English