LG 65UB930T Service Manual

URSA9 Block Diagram
SPI_CZ
SPI D
X-tal
URSA9
LGE7410
Panel
3840x2160@120
p
Serial
Flash(4MB)
SPI
_
D
O
SPI_CK
SPI_DI
XIN_URSA
XO_URSA
FLASH WP URSA
GPIO[25]
24MHz
1Gb x 4 (1600)
DDR3
16x4
Vx1 8Lane(12Lane_5K) 41P
FLASH
_
WP
_
URSA
[TXDBN0/P0~N7/P7_L]
Vx1 8Lane 51P
U14
4K@60p Vx1 8 Lane Video
1080p / 2160p Vx1 4 Lane OSD
[GPIO[15]]
URSA9_CONNECT
[GPIO[3]]
[GPIO[16]/[17]]
Vx1_LOCKn_O/V
[LOCKN D/Q]
[Tx_U14_0N/0P~7N/7P]
[Tx_U14_8N/8P~11N/11P]
[TXDAN0/P0~N7/P7_L]
L_DIM_EN
Vx1
8Lane
51P
[GPIO[16]/[17]]
[LOCKN
_
D/Q]
LOCKnIN/HTPDnIN
[VX1T LOCKN]
[I2CS_SDA/SCL]
I2CS_SDA/SCL
TCON_I2C_EN
[INT_R21/GPIO[41]]
(URSA Debug)
[SPI4_DI/DIM9/GPIO53]
[SPI4_CK/DIM8/GPIO52]
3D_EN
[GPIO[4/5]]
Data_Format_0/1
I2C_SCL1/SDA1
H1
3
LOCKn
_
IN/
HTPDn
_
IN
[VX1T
_
LOCKN]
[VX1T_HTDPN]
URSA_RESET_SOC
(H13D GPIO[26])
[RESET]
UART2_RX
GPIO[1]/[0]
[SPI4_DI/DIM9/GPIO53]
BIT[2/1/0]
UD V 1 L
수
UART2_TX
DIM5/GPIO[37]
DIM6/GPIO[38]
DIM7/GPIO[39]
URSA_BIT0/1/2
BIT[2/1/0]
UD
_
V
x
1
L
ane
수
0/0/0 4K@120P _16Lanes
0/0/1 4K@60P _ 8Lanes
0/1/0 5K@120P _ 20Lanes
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only

LG 65UB930T Specifications

General

Brand	LG
Model	65UB930T
Category	LED TV
Language	English