LG EV700 - Pin Configuration; Block Diagram

- 53 -
1
16
5
6
7
8
FBKG
INT
VSYNC
V
DD
HFLB(NC)
SS
SDA
(MOSI)
SCL
(SCK)
1
2
3
4
16
15
14
13
V
SS
R
G
B
V
SS(A)
VCO(PCI)
RP(NC)
V
DD(A)
12
11
10
9
LSC4543 CMOS Graphic Monitor On-Screen Display
DATA RECEIVER
MBUS/SPI
CHARACTER ROM (240
+16)
12 x 18 MATRIX
COLOR ENCODER
BUS ARBITRATION
LOGIC
ROW
BUFFER
BACKGROUND
GENEARTOR
1 0 BITS SHIFT
REGISTERS
VERTICAL
CONTROL
CIRCUIT
HORIZONTAL
CONTROL
and PLL
7
SDA(M0SI)
8SCL(SCK)
6
8
6
SS
3
RP(NC)
2VCO(PCI)
5
4
V
DD(A)
V
DD
9
16
1
V
SS(A)
V
SS
HFLB(NC)
10
CHAR
VSYNC
CHS
VPOL
HPOL
VERD
CH
RFG
NROW
MCLK
8
9
7
8
6
15
54
13
32
Z
8
RDATA
DATA
ADR
9
ADDRC
4
R
7
PWM_CLK
SC CCLK
8
CRADDR
4
LP
32
Y
WADDR
CHS
CWS
WCOLOR
and
CONTROL
CCOLORS
and SELECT
CCOLORS
and SELECT
CWS
DHOR MCLK
FBKG
INT
B
G
R
BLCKEDGE LUMINANCE
OSD_EN
SHADOW
BSEN
54
WADDR
X32B
X64
W
3
15
WCOLOR
and CONTROL
13
15 14 13 12 11
DISPLAY
MEMORY
CONTROL
REGISTERS
and DATA
MANAGEMENT
12 x 3
OSD_EN
HORD
VERO
CH
SHADOW
BSEN
X32B
X64
VPOL
HPOL
BLOCK DIAGRAM
Pin Configuration