LG HT353SD - Page 50

Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
2-41
5. IC704 PWM
• PIN CONFIGURATION
• BLOCK DIAGRAM
PLL
PWM
Modulator
Internal Controls
MLRCK
MBCK
MSDIN[0:3]
SCK/SCL
SO/SDA
SI/I2C_AD0
/
CS/I2C_AD2
PWM2_P/M
PWM3_P/M
PWM4_P/M
PWM5_P/M
PWM6_P
/M
/RESET
OVERLOAD
EXT_MUTE
PWM1_P/M
PWM8_P/M
Internal Clock
SPI/I2C
PWM7_P/M
SLRCK
SBCK
SSDIN[0:3]
PWM_HP_R_P/M
PWM_HP_L_P/M
EPD_ENA
PWM_
SWL_P/M
MIC_LRCK
MIC_BCK
MIC_SDIN
MIC_MC
LK
DMIX_MCLK
OLRCK
OBCK
DMIX_S
DOUT
PLL_DVDD
PLL_DVSS
PLL_AVDD
PLL_AVSS
DVDD
DVSS
IO_VDD
IO_V
SS
Power Supply
Reset & Po
wer Down
Internal Reset
Serial Audio
Output
interfac
e
Automatic
Gain
Limiter
Main
Volum
e
Trim
Volume
Bass
Manager
EQ
Down
Mixe
r
Mixe
r
Mic.
Input
Processo
r
Input
Mapper
Sample
Rate
Converte
r
Input
&
Output
MUX
Host
Interface
(I
2
C, SPI)
Serial
Audio
Output
inter
face
Output Mapper
POP
NR
Crystal
Oscillator
XI N
XO
UT
IO_VDD
PLL_DVDD
IO_VSS
IO_VSS
PLL_AVDD
IO_VSS
PLL_AVSS
PLL_DVSS
MLRCK
MBCK
MSDIN0
MIC_LRCK
MIC_BCK
MIC_MCLK
PWM_HP_R_P
IO_VSS PWM2_P PWM2_M PWM3_P PWM3_M PWM4_P PWM4_M
SPI/I2C
/CS/I2C_AD2
SI/I2C_AD0
SO/SDA
SCK/SCL
/RESET
SCAN_ENA
XIN
DVSS
IO_VSS
IO_VSS
IO_VSS
DVDD
DVSS
IO_VDD IO_VSS
MSDIN1 MSDIN2
SLRCK
SBCK
DVSS PWM5_P PWM5_M DVDD
TEST_MODE3
DVSS
IO_VSS PWM6_P PWM6_M IO_VSS
IO_VSS
PWM1_P
PWM1_M
OVERLOAD
IO_VSS
IO_VSS
SSDIN1
EXT_MUTE
DVDD
IO_VDD
DVDD
SSDIN0
MSDIN3
SSDIN2
SSDIN3
IO_VSS
IO_VDD
MIC_SDIN
PWM_SWL_P
PWM_SWL_M
PWM_HP_L_P
PWM_HP_L_M
PWM_HP_R_M
IO_VSS PWM7_P PWM7_M PWM8_P PWM8_M
EPD_ENA
TEST_MODE2
TEST_MODE1
IO_VSS
DMIX_LRCK
DMIX_BCK
DMIX_SDOUT
DMIX_MCL
K
9
8
9
9
1
0
0
9
6
9
7
9
3
9
4
9
5
9
1
9
2
8
5
8
6
8
7
8
8
8
9
9
0
8
3
8
4
8
1
8
2
71 72 73 74 75 61 62 63 64 65 66 67 68 69 70 53 54 55 56 57 58 59 51 52 60
46
47
48
49
50
9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8
30
31
32
33
34
35
36
37
26
27
28
29
7
6
7
7
7
8
7
9
8
0
17 18 19 20
38
39
40
41
42
43
44
45
21 22 23 24 25
IO_VDD
IO_VSS
IO_VDD
DVDD
DVSS
IO_VDD
IO_VDD IO_VDD
DVSS
DVDD
IO_VDD
PULSUS
XOUT