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LSI LSISAS3041E - Page 19

LSI LSISAS3041E
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PCI Performance 1-5
Version 1.0 Copyright © 2006 by LSI Logic Corporation. All rights reserved.
Contains a replay buffer that preserves a copy of the data for
retransmission in case a CRC error occurs
Supports the PCI Express Advanced Error Reporting capabilities
Uses a packetized and layered architecture
Achieves a high bandwidth per pin with low overhead and low latency
PCI Express is software compatible with PCI and PCI-X software
Leverages existing PCI device drivers
Supports the Memory, I/O, and Configuration address spaces
Supports memory read/write transactions, I/O read/write
transactions, and configuration read/write transactions
Provides 4 Kbytes of PCI Configuration address space per device
Supports posted and non-posted transactions
Provides quality of service (QOS) link configuration and arbitration
policies
Supports Traffic Class 0 and one virtual channel
Supports Message Signaled Interrupts (both MSI and MSI-X) as well
as INTx interrupt signaling for legacy PCI support
Supports end-to-end CRC (ECRC) and Advanced Error Reporting

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