1
2
3
5
4
SCL
GND
SDA
WP
VCC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead SOIC
8-ball dBGA2
8-lead Ultra-Thin
Mini-MAP (MLP 2x3)
8-lead PDIP
5-lead SOT23
Bottom View Bottom View
8-lead TSSOP
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (V
CC
= 1.8V to 5.5V)
• Internally Organized 512 x 8 (4K), or 1024 x 8 (8K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 16-byte Page (4K, 8K) Write Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers
Description
The AT24C04B/08B provides 4096/8192 bits of serial electrically erasable and pro-
grammable read-only memory (EEPROM) organized as 512/1024 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT24C04B/08B is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-
MAP (MLP 2x3)
, 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is
accessed via a Two-wire serial interface. In addition, the AT24C04B/08B is available
in 1.8V (1.8V to 5.5V) version.
Table 0-1. Pin Configuration
Pin Name Function
A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
GND Ground
VCC Power Supply
Two-wire
Serial EEPROM
4K (512 x 8)
8K (1024 x 8)
AT24C04B
AT24C08B
Preliminary
5226B–SEEPR–8/07
Note: For use of 5-lead SOT23
4K: The software A2 and A1 bits in
the device address word must be set
to zero to properly communicate.
8K: The software A2 bit in the device
address word must be set to zero to
properly communicate.
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