Marantz SR7300 - Page 27

39
Pin Assignment
Block Diagram
124V
REF
SYR
223MPXIN CE
322Vdda DI
421Vssa CL
520FLOUT DO
619CIN
LC72722
LC72722M
LC72722PM
Top view
RDS-ID
718T1 SYNC
817T2 T7(CORREC/ARI-ID/TA/BEO)
916
T
3(RDCL) T6(ERROR/57K/TP/BE1)
10 15
T
4(RDDA) Vssd
11 14
T
5(RSFT) Vddd
12 13X
OUT
X
IN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
SMOOTHING
FILTER
57 kHz
BPF
(SCF)
TEST
+
–
PLL
(57 kHz)
V
REF
CLOCK
RECOVERY
(1187.5 Hz)
DATA
DECODER
SYNC
DETECT-2
SYNC
DETECT-1
OSC/DIVIDER
MEMORY CONTROL
CLK(4.332 MHz)
+5V +5V
Vdda
Vssa
MPXIN
T2
T3 to T7
T1
CCB
DI
CE
CL
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
SYNC/EC CONTROLLER
DO
X
IN
X
OUT
SYR
SYNC
RDS-ID
Vssd
Vddd
CINFLOUT
V
REF
Pin Functions
Pin No. Pin name Function
1 VREF Reference voltage output (Vdda/2)
2 MPXIN Baseband (multiplexed) signal input
5 FLOUT Subcarrier output (filter output)
6 CIN Subcarrier input (comparator input)
3 Vdda Analog system power supply (+5 V)
4 Vssa Analog system ground
12 XOUT Crystal oscillator output (4.332/8.664 MHz)
13 XIN Crystal oscillator input (external reference signal input)
7 T1 Test input (This pin must always be connected to ground.)
8T2
Test input (standby control)
0: Normal operation, 1: Standby state (crystal oscillator stopped)
9 T3 (RDCL) Test I/O (RDS clock output)
10 T4 (RDDA) Test I/O (RDS data output)
11 T5 (RSFT) Test I/O (soft-decision control data output)
16
T6 (ERROR/
57K/TP/BE1)
Test I/O (error status output, regenerated carrier output,
TP output, error block count output)
17
T7 (CORREC/
ARI-ID/TA/BE0)
Test I/O (Error correction status output, SK detection output,
TA output, error block count output)
18 SYNC Block synchronization detection output
19 RDS-ID RDS detection output
20 DO Data output
21 CL Clock input
22 DI Data input
23 CE Chip enable
24 SYR Synchronization and RAM address reset (active high)
14 Vddd Digital system power supply (+5 V)
15 Vssd Digital system ground
Note: * Normally function as an output pin. Used as an I/O pin in test mode,
which is not available to user applications.
Serial data interface (CCB)
Input
Input
Output
I/O
Input
Output
Input
—
—
Output
Input
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
Output
Output
Input
Input
Input
Input
—
—
Q901 : LC72722
99 MCLK Audio Master Clock
100 VDD2 2.5V Supply Voltage
101 VSS2 2.5V Ground
102 I/O AUDATA4,
GPIO28
Digital Audio Output 4, General Purpose I/O
103 I/O HDATA4,
GPIO4
DSP C Bidirectional Data Bus, General Purpose I/O
104 O SCLK0 Audio Output Bit Clock
105 I/O HDATA3,
GPIO3
DSP C Bidirectional Data Bus, General Purpose I/O
106 O AUDATA3,
XMT958A
Digital Audio Output 3, S/PDIF Transmitter
107 O AUDATA2 Digital Audio Output 2
108 O LRCLK0 Audio Output Sample Rate Clock
109 O AUDATA1 Digital Audio Output 1
110 O AUDATA0 Digital Audio Output 0
111 I CMPCLK,
FSCLKN2
PCM Audio Input Bit Clock
112 I/O HDATA2,
GPIO2
DSP C Bidirectional Data Bus, General Purpose I/O
113 VSS3 2.5V Ground
114 VDD3 2.5V Supply Voltage
115 I/O HDATA1,
GPIO1
DSP C Bidirectional Data Bus, General Purpose I/O
116 I/O HDATA0,
GPIO0
DSP C Bidirectional Data Bus, General Purpose I/O
117 O CMPREQ,
FLRCLKN2
Frame Clock Data Request Out
118 I CMPDAT,
FSDATAN2
PCM Audio Data Input Number Two
119 I FLRCLKN1 PCM Audio Input Sample Rate Clock
120 I/O WR, DS,
GPIO10
Host Write Strobe, Host Data Strobe, General Purpose I/O
121 I/O RD, R/W,
GPIO11
Host Parallel Output Enable, Host Parallel R/W, General
Purpose I/O
122 PLLVSS PLL Ground Voltage
123 FILT2 Phase Locked Loop Filter
124 FILT1 Phase-Locked Loop Filter
125 PLLVDD PLL Supply Voltage
126 O CLKOUT,
XTALO
Crystal Oscillator Output
127 I CLKIN, XTALI External Clock Input/Crystal Oscillator Input
128 CLKSEL DSP Clock Select
129 I/O CS, GPIO9 Host Parallel Chip Select, General Purpose I/O
130 I/O A0, GPIO13 Host Parallel Address Bit 0, General Purpose I/O
131 I FSDATAN1 PCM Audio Data Input One
132 VDD4 2.5V Supply Voltage
133 VSS4 2.5V Ground
134 I FSCLKN1,
STCCLK2
PCM Audio Input Bit Clock
135 SCS Host Serial SPI Chip Select
136 I SCDIN SPI Serial Control Data Input
137 VSS5 2.5V Ground
138 VDD5 2.5V Supply Voltage
139 I/O A1, GPIO12 Host Address Bit 1, General Purpose I/O
140 I/O SCDOUT,
SCDIO
Serial Control Port Data Input and Output
141 I/O HINBSY,
GPIO8
Input Host Message Status, General Purpose I/O
142 SCCLK Serial Control Port Clock
143 I/O UHS2,
CS_OUT,
GPIO17
Mode Select Bit 2, External Serial Memory Chip Select,
General Purpose I/O
144 I RESET Master Reset Input
Q901 : LC72722
Q600 : CS494001-CQ
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