STANDARD
EVENT REGISTERS
This Register is defined by IEEE 488.2 and each bit has the meaning shown below:-
Condition
.......
Register
d
7
d
6
d
5
d
4
d
3
d
z
d
(
d
c
<esb>
#
Positive
transition sets status. C0069
<pon> power on
<urq> user request
-
not implemented in this product
<cme> command error
<exe> execution error
<dde> device dependent error
<qye>
query error
<rqc> request control
-
not implemented in this product
<opc>
operation
complete
-
set in response to the *OPC command for
synchronisation.
<esb> standard event register summary bit
46882-074C
3-2-43
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