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STATUS BYTE
WHEN READ BY *STB?
Register
Read
d
7
Status Byte Register
d
4
d
3
d
2
d,
Read/Write
Service Request Enable Register#
Commands
# Bit 6 in this register ignores data sent by *SRE and always returns 0
in response
to
*SRE?
C0073
<rqs>, <esb> and <mav> are defined in IEEE 488.2
<erb> is
a
device defined
queue
summary bit indicating that the error queue is non-empty.
<mss> is true when (Status Byte) AND (Enable register)
>
0.
<esb>
is the standard event register summary bit.
<mav> is 'message available
1
indicating that
the output queue is
non-empty.
<hsb>
is 'hardware status' summary bit
<csb> is 'coupling status'
summary
bit
<ssb>
is 'instrument status' summary bit
Note...
The Status Byte Register is Not cleared by the *STB? query.
3-2-48
46882-074C
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