PICkit™ 3 STARTER KIT USER’S GUIDE
2012 Microchip Technology Inc. DS41628B-page 17
Chapter 2. PIC
®
MCU Architecture
2.1 INTRODUCTION
This chapter describes the architecture of the enhanced mid-range PIC16F1829
(DS41440), as well as the PIC18 (DS41365).
2.2 CORE BASICS
Enhanced PIC16 and PIC18 devices use a modified Harvard architecture, meaning the
code memory and data memory are independent. This allows faster execution because
code instructions and data can be accessed simultaneously. The subsequent instruc-
tion is fetched while decoding and executing the current instruction. In Figure 2-1 and
Figure 2-3, the reader should notice the separate lines for data bus and program bus.
This guide will cover nearly all of the registers and modules as seen in the following
figures. The following block diagrams should be referenced while each lesson is being
performed in order to understand the interactions.
FIGURE 2-1: SIMPLIFIED ENHANCED MID-RANGE PIC
®
MCU BLOCK DIAGRAM
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
V
SS
Internal
Oscillator
Block
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
V
SS
Internal
Oscillator
Block
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
V
SS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
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