PIC® MCU Architecture
2012 Microchip Technology Inc. DS41628B-page 21
2.6 BYTE
All byte instructions on the enhanced PIC16 contain a 6-bit opcode, 7-bit file address,
and a destination bit. All PIC18 byte instructions contain a 6-bit opcode, 8-bit file
address, a destination bit, and a RAM access bit.The sum of all the bit field sizes con-
firms that the PIC16 enhanced core does indeed have a 14-bit wide word size for
instructions. Likewise, the same can be seen for the PIC18 for its 16-bit wide word
length.
The RAM access bit (a) on the PIC18 is set when the user wishes to use the Bank
Select Register (BSR) for manually selecting the bank. The PIC16 user will always
need to make sure that they are in the correct bank by using the ‘banksel’ directive.
This is explained in the first few lessons.
The destination bit (d) specifies whether the result will be stored in WREG or back in
the original file register. When ‘d’ is zero, the result is placed in the WREG resister.
Otherwise, the result is placed in the file register.
The file register (f) specifies which register to use. This can be a Special Function
Register (SFR) or General Purpose Register (GPR).
EXAMPLE 2-2:
This adds the contents of WREG and data, with the result being saved back to the file
register data.
The PIC18 can move data from one file register directly to another file register, circum-
venting the WREG. All file moves in the enhanced PIC16 architecture must go through
the WREG.
2.7 BIT
Bit instructions operate on a specific bit within a file register. These instructions may set
or clear a specific bit within a file register. They may also be used to test a specific bit
within a file register. All bit instructions on the enhanced PIC16 contain a 4-bit opcode,
7-bit file address, and a 3-bit bit address. All PIC18 byte instructions contain a 4-bit
opcode, 8-bit file address, 3-bit bit address and a RAM access bit.
EXAMPLE 2-3:
This sets pin RA0 in the PORTA register.
2.8 LITERAL
Literal operations contain the data operand within the instruction. Both architectures
use an 8-bit intermediate value. The rest of the bits are reserved for the opcode.
EXAMPLE 2-4:
This moves the ASCII value of ‘A’ (0x41) into WREG.
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