PICkit™ 3 Starter Kit User’s Guide
DS41628B-page 74 2012 Microchip Technology Inc.
3.11 LESSON 10: INTERRUPTS AND PULL-UPS
3.11.1 Introduction
This lesson introduces interrupts and how they are useful. It also introduces internal
weak pull-ups that are available on most PIC devices. This lesson expands on the pre-
vious lessons, but mostly Lessons 9 and 3.
3.11.2 Hardware Effects
LEDs rotate at a constant speed and the switch reverses their direction.
3.11.3 Summary
Two new concepts are introduced: interrupts and weak pull-ups.
3.11.3.1 INTERRUPTS
The interrupt feature allows certain events to preempt normal program flow. This
means that the microcontroller can be configured to be aware of its surroundings. Rou-
tines can be run upon some external event. Firmware is used to determine the source
of the interrupt and act accordingly. All interrupts can be configured to wake the MCU
from Sleep mode.
Most of the peripherals can generate an interrupt. Some of the I/O pins may be config-
ured to generate an interrupt when they change state. When a peripheral needs ser-
vice, it sets its interrupt flag. Each interrupt flag is ANDed with its enable bit and then
these are ORed together to form a master interrupt. This master interrupt is ANDed with
the Global Interrupt Enable (GIE). The enable bits allow the PIC microcontroller to limit
the interrupt sources to certain peripherals. See the Interrupt Logic Figure in the PIC
microcontroller data sheet for a drawing of the interrupt logic. Below is a simplified dia-
gram.
FIGURE 3-11: SUMMARY OF INTERRUPT FLOW
The PIC18 has a slightly different structure to accommodate interrupt priority. The
enhanced mid-range core has only one interrupt vector. This means that whenever an
interrupt occurs, the program counter goes to the interrupt service address, specifically
address 0x0004. The PIC18 allows most interrupt sources to be assigned a high or low
priority level. The high priority vector is at 0x0008 and the low at 0x0018. A high priority
interrupt event will interrupt a low priority that may be in progress. This lesson will not
utilize priority interrupts and will instead make use of the mid-range compatibility fea-
ture by clearing the IPEN bit. Both devices will now service from only one vector.
When an interrupt is responded to, the Global Interrupt Enable (GIE) bit is cleared to
disable further interrupts. The return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. Both the enhanced mid-range and PIC18
devices perform automatic context saving for the WREG, STATUS, and BSR registers.
The FSR and PCLATH registers are saved only in the enhanced mid-range devices.
The PIC18 requires a retfie, fast instruction execution to restore the context.
Ms
Global Interrupt Enable
Other Interrupt Sources
Interrupt Flag
Interrupt Enable
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