PICkit™ 3 Starter Kit User’s Guide
DS41628B-page 28 2012 Microchip Technology Inc.
2.13.1 Core Registers
The core registers contain the registers that directly affect the basic operation of the
PIC device, repeated at the top of every data memory bank. Here are three examples
of the 12 core registers:
1. STATUS
2. WREG
3. INTCON
The STATUS register contains the arithmetic status of the ALU. The WREG register is
used to move bits in and out of registers. The INTCON register contains the various
enable and flag bits that would cause the PIC MCU to jump to the Interrupt Vector.
2.13.2 Special Function Registers
The Special Function Registers provide access to the peripheral functions in the
device. The Special Function Registers occupy 20 bytes immediately after the core reg-
isters of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh) on the
enhanced mid-range core. The PIC18 enhanced core has all of its SFRs in Access
RAM, which is discussed in Section 2.14 “Banks”.
2.13.3 General Purpose RAM
GPRs are used for data storage and scratchpad operations in the user’s application.
Think of this as RAM that can be used for your program, but the correct bank must be
selected before using. For the enhanced mid-range PIC devices, there are up to 80
bytes of GPR that follow immediately after the SFR space in each data memory bank.
2.13.4 Common RAM
There are 16 bytes of common RAM accessible from all banks in the enhanced core.
The PIC18 architecture has something similar called Access RAM, which contains up
to 96 bytes.
2.14 BANKS
The PIC18F14K22 data memory is divided into 16 banks that contain 256 bytes each.
The PIC16F1829 data memory is partitioned in 32 memory banks with 128 bytes in
each bank. For the PIC16 enhanced mid-range, each bank consists of:
1. 12 core registers
2. 20 Special Function Registers (SFR)
3. Up to 80 bytes of General Purpose RAM (GPR)
4. 16 bytes of shared RAM (accessible by any bank)
Figure 2-8 shows the above information on the enhanced PIC16.
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